Reviewed-by: kvn

Reviewed-by: kvn

Reviewed-by: kvn, mdoerr

Reviewed-by: kvn, mdoerr

Summary: Add intrinsics for BigInteger squareToLen and mulAdd methods.
Reviewed-by: kvn, jrose

Summary: Add intrinsics for BigInteger squareToLen and mulAdd methods.
Reviewed-by: kvn, jrose

Summary: Require to specify UnlockExperimentalVMOptions flag together with UseRTMLocking flag on un-patched systems where CPUID allows it but is unsupported otherwise.
Reviewed-by: iveresov, fzhinkin

Summary: Add C2 SHA intrinsics on SPARC
Reviewed-by: kvn, roland
Contributed-by: james.cheng@oracle.com

Summary: Allow to execute vectorization and crc32 optimization on Atom. Enable UseFPUForSpilling by default on x86.
Reviewed-by: roland

8043029: Change 8037816 breaks HS build with older GCC versions which don't support diagnostic pragmas
8043164: Format warning in traceStream.hpp
Summary: Backport of main fix + two corrections, enables clang compilation, turns on format attributes, corrects/mutes warnings
Reviewed-by: kvn, coleenp, iveresov, twisti

Summary: temporary set UseAVX=1 and UseSSE=2 in generate_get_cpu_info()
Reviewed-by: twisti

Summary: verify YMM registers after signal processing and set limit on vector's size.
Reviewed-by: iveresov, twisti

Summary: Add support for BMI1 instructions
Reviewed-by: kvn, roland

Summary: Add new C2 intrinsic for BigInteger::multiplyToLen() on x86 in 64-bit VM.
Reviewed-by: roland

Summary: Use RTM for inflated locks and stack locks.
Reviewed-by: iveresov, twisti, roland, dcubed

8059139: It should be possible to explicitly disable usage of TZCNT instr w/ -XX:-UseBMI1Instructions
Reviewed-by: iveresov

Summary: Windows need an exception wrapper around getPsrInfo_stub() call in order to properly handle SEGV for YMM registers test.
Reviewed-by: iveresov, iignatyev

Summary: add intrinsics using new instruction to interpreter, C1, C2, for suitable x86; add test
Reviewed-by: kvn, twisti

Summary: Limit vectors size to 16 bytes on BSD until the problem is fixed
Reviewed-by: twisti

Summary: HotSpot changes to support @Contended annotation.
Reviewed-by: coleenp, kvn, jrose
Contributed-by: NAleksey Shipilev <aleksey.shipilev@oracle.com>

Summary: use 'rep stosb' instead of 'rep stosq' when fast-string operations are available.
Reviewed-by: twisti, roland

Summary: Enable AES intrinsics on non-AVX cpus, group together aes instructions in crypto stubs.
Reviewed-by: roland, twisti

Reviewed-by: kvn

Summary: Add missing UseSSE check for AES intrinsics.
Reviewed-by: roland, twisti

Summary: Use new x86 AES instructions for AESCrypt.
Reviewed-by: twisti, kvn, roland
Contributed-by: tom.deneau@amd.com

Summary: renamed mach nodes which use scalar AVX instructions, added integer vectors shuffling instructions
Reviewed-by: twisti

Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland

Summary: use shorter instruction sequences for atomic add and atomic exchange when possible.
Reviewed-by: kvn, jrose

Summary: Fixed vectors alignment when several arrays are accessed in one loop.
Reviewed-by: roland, twisti

Summary: Change OSThread to use mach thread_t
Reviewed-by: phh, dcubed

Summary: Add rdtsc detection and inline generation.
Reviewed-by: kamg, dholmes
Contributed-by: karen.kinnear@oracle.com

Summary: Added support for AVX extension to the x86 instruction set.
Reviewed-by: never

Reviewed-by: kvn, twisti, jrose
Contributed-by: NKurt Miller &lt;kurt@intricatesoftware.com&gt;, Greg Lewis &lt;glewis@eyesbeyond.com&gt;, Jung-uk Kim &lt;jkim@freebsd.org&gt;, Christos Zoulas &lt;christos@zoulas.com&gt;, Landon Fuller &lt;landonf@plausible.coop&gt;, The FreeBSD Foundation &lt;board@freebsdfoundation.org&gt;, Michael Franz &lt;mvfranz@gmail.com&gt;, Roger Hoover &lt;rhoover@apple.com&gt;, Alexander Strange <astrange@apple.com>

Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Summary: correct Icache::line_size for x64 and add verification code into vm_version_x86.
Reviewed-by: never, phh

Summary: use PREFETCHW as default prefetch instruction, set UseXMMForArrayCopy and UseUnalignedLoadStores to true by default.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

7044486: open jdk repos have files with incorrect copyright headers, which can end up in src bundles
Reviewed-by: ohair, trims

Summary: The upcoming processors from AMD are the first that support 3dnow prefetch without supporting the 3dnow instruction set.
Reviewed-by: kvn
Contributed-by: tom.deneau@amd.com

7010070: Update all 2010 Oracle-changed OpenJDK files to have the proper copyright dates - second pass
Summary: Update the copyright to be 2010 on all changed files in OpenJDK
Reviewed-by: ohair

Summary: New AMD processors support sse4.2. Enable corresponding instructions in Hotspot.
Reviewed-by: kvn
Contributed-by: eric.caspole@amd.com