Summary: Fix the arbitrary alignment issue in SPARC AES crypto stub routines.
Reviewed-by: kvn, iveresov
Contributed-by: shrinivas.joshi@oracle.com

Summary: Add intrinsics/stub routines support for single-block and multi-block (as used by Cipher Block Chaining mode) AES encryption and decryption operations on the SPARC platform.
Reviewed-by: kvn, roland
Contributed-by: shrinivas.joshi@oracle.com

Summary: Copyright year updated for files modified during 2013
Reviewed-by: twisti, iveresov

Summary: fix code to allow testing on Fujitsu Sparc64 CPUs
Reviewed-by: kvn

Summary: Removed most of the SPARC V8 instructions
Reviewed-by: kvn, twisti

Summary: HotSpot changes to support @Contended annotation.
Reviewed-by: coleenp, kvn, jrose
Contributed-by: NAleksey Shipilev <aleksey.shipilev@oracle.com>

Reviewed-by: jrose, kvn

Summary: support of compress class pointers in the compilers.
Reviewed-by: kvn, twisti

Summary: G1 does not appear to be immune to the issue described in CR 6948537 and increasing the size of old-generation PLABs appears to increase the liklihood of seeing the issue. Extend the fix for 6948537 to G1's BlockOffsetTable.
Reviewed-by: brutisso, jmasa

Summary: Increase vector size up to 256-bits for YMM AVX registers on x86.
Reviewed-by: never, twisti, roland

Reviewed-by: kvn
Contributed-by: NTao Mao <tao.mao@oracle.com>

Summary: use shorter instruction sequences for atomic add and atomic exchange when possible.
Reviewed-by: kvn, jrose

Reviewed-by: never, kvn

Summary: Use BIS and prefetch in arraycopy stubs for Sparc (BIS for T4 only).
Reviewed-by: never, iveresov

Summary: Use BIS for zeroing new allocated big (2Kb and more) objects and arrays.
Reviewed-by: never, twisti, ysr

Summary: on T4 2 BIS instructions should be issued to prefetch 64 bytes
Reviewed-by: iveresov, phh, twisti

Summary: Use new short branch instruction in C2 generated code.
Reviewed-by: never

Summary: Add new short branch instruction to Hotspot sparc assembler.
Reviewed-by: never, twisti, jrose

Summary: Use new VIS3 mov instructions on T4 for move data between general and float registers.
Reviewed-by: never, twisti

Summary: read Solaris kstat data to get more precise CPU information
Reviewed-by: iveresov, never, twisti, dholmes

Summary: Replaced MakeDeps and the includeDB files with more standardized solutions.
Reviewed-by: coleenp, kvn, kamg

Summary: Use hardware DIV instruction for long division by constant when it is faster than code with multiply.
Reviewed-by: never

Reviewed-by: kvn

Summary: Hoist DecodeN instruction above null check
Reviewed-by: never, twisti

Summary: Change all the Sun copyrights to Oracle copyright
Reviewed-by: ohair

Summary: On sun4v/CMT avoid use of memset() in BOT updates so as to prevent concurrent BOT readers from seeing the phantom zeros arising from memset()'s use of BIS.
Reviewed-by: jmasa, johnc, minqi, poonam, tonyp

Summary: Use BIS instruction for allocation prefetch on Sparc
Reviewed-by: twisti

Summary: Don't align loops in stubs for Niagara sparc since NOPs are expensive.
Reviewed-by: twisti, never

Summary: Tune C2 flags default values for performance.
Reviewed-by: never, phh, iveresov, jmasa, ysr

Summary: bitCount() should use POPC on SPARC processors where POPC is implemented directly in hardware.
Reviewed-by: kvn, never

Summary: Use zero based compressed oops if java heap is below 32gb and unscaled compressed oops if java heap is below 4gb.
Reviewed-by: never, twisti, jcoomes, coleenp

Summary: A similar function to getisax(2) should be used to determine all possible instruction set extensions.
Reviewed-by: never, kvn

Summary: Update copyright year for files that have been modified in 2008
Reviewed-by: ohair, tbell

Summary: Compressed oops in instances, arrays, and headers. Code contributors are coleenp, phh, never, swamyv
Reviewed-by: jmasa, kamg, acorn, tbell, kvn, rasbold

Summary: Use the same default number of GC threads as used by ParNewGC and ConcMarkSweepGC (i.e., the 5/8th rule).
Reviewed-by: ysr, tonyp