提交 fe72f302 编写于 作者: D dlong

8001101: C2: more general vector rule subsetting

Summary: Allow which vector rules are supported to be decided at runtime. Also a small change to allow vector types in Type::_type_info[] to apply to more platforms.
Reviewed-by: kvn, twisti
Contributed-by: dean.long@oracle.com
上级 d8cad725
...@@ -61,7 +61,7 @@ Type::TypeInfo Type::_type_info[Type::lastype] = { ...@@ -61,7 +61,7 @@ Type::TypeInfo Type::_type_info[Type::lastype] = {
{ Bad, T_ILLEGAL, "tuple:", false, Node::NotAMachineReg, relocInfo::none }, // Tuple { Bad, T_ILLEGAL, "tuple:", false, Node::NotAMachineReg, relocInfo::none }, // Tuple
{ Bad, T_ARRAY, "array:", false, Node::NotAMachineReg, relocInfo::none }, // Array { Bad, T_ARRAY, "array:", false, Node::NotAMachineReg, relocInfo::none }, // Array
#if defined(IA32) || defined(AMD64) #ifndef SPARC
{ Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS { Bad, T_ILLEGAL, "vectors:", false, Op_VecS, relocInfo::none }, // VectorS
{ Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD { Bad, T_ILLEGAL, "vectord:", false, Op_VecD, relocInfo::none }, // VectorD
{ Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX { Bad, T_ILLEGAL, "vectorx:", false, Op_VecX, relocInfo::none }, // VectorX
......
...@@ -29,8 +29,7 @@ ...@@ -29,8 +29,7 @@
//------------------------------VectorNode-------------------------------------- //------------------------------VectorNode--------------------------------------
// Return the vector operator for the specified scalar operation // Return the vector operator for the specified scalar operation
// and vector length. Also used to check if the code generator // and vector length.
// supports the vector operation.
int VectorNode::opcode(int sopc, BasicType bt) { int VectorNode::opcode(int sopc, BasicType bt) {
switch (sopc) { switch (sopc) {
case Op_AddI: case Op_AddI:
...@@ -75,7 +74,7 @@ int VectorNode::opcode(int sopc, BasicType bt) { ...@@ -75,7 +74,7 @@ int VectorNode::opcode(int sopc, BasicType bt) {
case T_BYTE: return 0; // Unimplemented case T_BYTE: return 0; // Unimplemented
case T_CHAR: case T_CHAR:
case T_SHORT: return Op_MulVS; case T_SHORT: return Op_MulVS;
case T_INT: return Matcher::match_rule_supported(Op_MulVI) ? Op_MulVI : 0; // SSE4_1 case T_INT: return Op_MulVI;
} }
ShouldNotReachHere(); ShouldNotReachHere();
case Op_MulF: case Op_MulF:
...@@ -157,12 +156,14 @@ int VectorNode::opcode(int sopc, BasicType bt) { ...@@ -157,12 +156,14 @@ int VectorNode::opcode(int sopc, BasicType bt) {
return 0; // Unimplemented return 0; // Unimplemented
} }
// Also used to check if the code generator
// supports the vector operation.
bool VectorNode::implemented(int opc, uint vlen, BasicType bt) { bool VectorNode::implemented(int opc, uint vlen, BasicType bt) {
if (is_java_primitive(bt) && if (is_java_primitive(bt) &&
(vlen > 1) && is_power_of_2(vlen) && (vlen > 1) && is_power_of_2(vlen) &&
Matcher::vector_size_supported(bt, vlen)) { Matcher::vector_size_supported(bt, vlen)) {
int vopc = VectorNode::opcode(opc, bt); int vopc = VectorNode::opcode(opc, bt);
return vopc > 0 && Matcher::has_match_rule(vopc); return vopc > 0 && Matcher::match_rule_supported(vopc);
} }
return false; return false;
} }
......
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