提交 aae2813b 编写于 作者: M mchinnathamb

8158012: Use SW prefetch instructions instead of BIS for allocation prefetches on SPARC Core C4

Reviewed-by: kvn, dholmes, poonam
上级 a14567db
/* /*
* Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
...@@ -140,10 +140,17 @@ void VM_Version::initialize() { ...@@ -140,10 +140,17 @@ void VM_Version::initialize() {
if (is_niagara_plus()) { if (is_niagara_plus()) {
if (has_blk_init() && (cache_line_size > 0) && UseTLAB && if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
// Use BIS instruction for TLAB allocation prefetch. if (!has_sparc5_instr()) {
FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1); // Use BIS instruction for TLAB allocation prefetch
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { // on Niagara plus processors other than those based on CoreS4.
FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3); FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
} else {
// On CoreS4 processors use prefetch instruction
// to avoid partial RAW issue, also use prefetch style 3.
FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
}
} }
if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) { if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
// Use smaller prefetch distance with BIS // Use smaller prefetch distance with BIS
...@@ -165,6 +172,11 @@ void VM_Version::initialize() { ...@@ -165,6 +172,11 @@ void VM_Version::initialize() {
FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256); FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
} }
if (AllocatePrefetchInstr == 1) { if (AllocatePrefetchInstr == 1) {
// Use allocation prefetch style 3 because BIS instructions
// require aligned memory addresses.
FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
// Need a space at the end of TLAB for BIS since it // Need a space at the end of TLAB for BIS since it
// will fault when accessing memory outside of heap. // will fault when accessing memory outside of heap.
......
/* /*
* Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved. * Copyright (c) 2005, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* *
* This code is free software; you can redistribute it and/or modify it * This code is free software; you can redistribute it and/or modify it
...@@ -1775,7 +1775,7 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false, ...@@ -1775,7 +1775,7 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false,
i_o = pf_phi_abio; i_o = pf_phi_abio;
} else if( UseTLAB && AllocatePrefetchStyle == 3 ) { } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
// Insert a prefetch for each allocation. // Insert a prefetch for each allocation.
// This code is used for Sparc with BIS. // This code is used to generate 1 prefetch instruction per cache line.
Node *pf_region = new (C) RegionNode(3); Node *pf_region = new (C) RegionNode(3);
Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY, Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
TypeRawPtr::BOTTOM ); TypeRawPtr::BOTTOM );
...@@ -1791,6 +1791,8 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false, ...@@ -1791,6 +1791,8 @@ Node* PhaseMacroExpand::prefetch_allocation(Node* i_o, Node*& needgc_false,
transform_later(cache_adr); transform_later(cache_adr);
cache_adr = new (C) CastP2XNode(needgc_false, cache_adr); cache_adr = new (C) CastP2XNode(needgc_false, cache_adr);
transform_later(cache_adr); transform_later(cache_adr);
// Address is aligned to execute prefetch to the beginning of cache line size
// (it is important when BIS instruction is used on SPARC as prefetch).
Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1)); Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
cache_adr = new (C) AndXNode(cache_adr, mask); cache_adr = new (C) AndXNode(cache_adr, mask);
transform_later(cache_adr); transform_later(cache_adr);
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册