提交 2d52ec7b 编写于 作者: N never

7004940: CTW: assert(!def_outside->member(r)) failed: Use of external LRG overlaps the same LRG

Reviewed-by: kvn, twisti
上级 7888ef8c
...@@ -1782,7 +1782,7 @@ void PhaseChaitin::dump() const { ...@@ -1782,7 +1782,7 @@ void PhaseChaitin::dump() const {
for(uint i2 = 1; i2 < _maxlrg; i2++ ) { for(uint i2 = 1; i2 < _maxlrg; i2++ ) {
tty->print("L%d: ",i2); tty->print("L%d: ",i2);
if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( ); if( i2 < _ifg->_maxlrg ) lrgs(i2).dump( );
else tty->print("new LRG"); else tty->print_cr("new LRG");
} }
tty->print_cr(""); tty->print_cr("");
...@@ -1993,7 +1993,7 @@ void PhaseChaitin::dump_bb( uint pre_order ) const { ...@@ -1993,7 +1993,7 @@ void PhaseChaitin::dump_bb( uint pre_order ) const {
} }
//------------------------------dump_lrg--------------------------------------- //------------------------------dump_lrg---------------------------------------
void PhaseChaitin::dump_lrg( uint lidx ) const { void PhaseChaitin::dump_lrg( uint lidx, bool defs_only ) const {
tty->print_cr("---dump of L%d---",lidx); tty->print_cr("---dump of L%d---",lidx);
if( _ifg ) { if( _ifg ) {
...@@ -2002,9 +2002,11 @@ void PhaseChaitin::dump_lrg( uint lidx ) const { ...@@ -2002,9 +2002,11 @@ void PhaseChaitin::dump_lrg( uint lidx ) const {
return; return;
} }
tty->print("L%d: ",lidx); tty->print("L%d: ",lidx);
lrgs(lidx).dump( ); if( lidx < _ifg->_maxlrg ) lrgs(lidx).dump( );
else tty->print_cr("new LRG");
} }
if( _ifg ) { tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx)); if( _ifg && lidx < _ifg->_maxlrg) {
tty->print("Neighbors: %d - ", _ifg->neighbor_cnt(lidx));
_ifg->neighbors(lidx)->dump(); _ifg->neighbors(lidx)->dump();
tty->cr(); tty->cr();
} }
...@@ -2024,16 +2026,18 @@ void PhaseChaitin::dump_lrg( uint lidx ) const { ...@@ -2024,16 +2026,18 @@ void PhaseChaitin::dump_lrg( uint lidx ) const {
dump(n); dump(n);
continue; continue;
} }
uint cnt = n->req(); if (!defs_only) {
for( uint k = 1; k < cnt; k++ ) { uint cnt = n->req();
Node *m = n->in(k); for( uint k = 1; k < cnt; k++ ) {
if (!m) continue; // be robust in the dumper Node *m = n->in(k);
if( Find_const(m) == lidx ) { if (!m) continue; // be robust in the dumper
if( !dump_once++ ) { if( Find_const(m) == lidx ) {
tty->cr(); if( !dump_once++ ) {
b->dump_head( &_cfg._bbs ); tty->cr();
b->dump_head( &_cfg._bbs );
}
dump(n);
} }
dump(n);
} }
} }
} }
......
...@@ -512,7 +512,11 @@ private: ...@@ -512,7 +512,11 @@ private:
void dump( const Block * b ) const; void dump( const Block * b ) const;
void dump_degree_lists() const; void dump_degree_lists() const;
void dump_simplified() const; void dump_simplified() const;
void dump_lrg( uint lidx ) const; void dump_lrg( uint lidx, bool defs_only) const;
void dump_lrg( uint lidx) const {
// dump defs and uses by default
dump_lrg(lidx, false);
}
void dump_bb( uint pre_order ) const; void dump_bb( uint pre_order ) const;
// Verify that base pointers and derived pointers are still sane // Verify that base pointers and derived pointers are still sane
......
...@@ -1239,6 +1239,7 @@ uint PhaseChaitin::Split( uint maxlrg ) { ...@@ -1239,6 +1239,7 @@ uint PhaseChaitin::Split( uint maxlrg ) {
// Cycle through this block's predecessors, collecting Reaches // Cycle through this block's predecessors, collecting Reaches
// info for each spilled LRG and update edges. // info for each spilled LRG and update edges.
// Walk the phis list to patch inputs, split phis, and name phis // Walk the phis list to patch inputs, split phis, and name phis
uint lrgs_before_phi_split = maxlrg;
for( insidx = 0; insidx < phis->size(); insidx++ ) { for( insidx = 0; insidx < phis->size(); insidx++ ) {
Node *phi = phis->at(insidx); Node *phi = phis->at(insidx);
assert(phi->is_Phi(),"This list must only contain Phi Nodes"); assert(phi->is_Phi(),"This list must only contain Phi Nodes");
...@@ -1273,7 +1274,16 @@ uint PhaseChaitin::Split( uint maxlrg ) { ...@@ -1273,7 +1274,16 @@ uint PhaseChaitin::Split( uint maxlrg ) {
assert( def, "must have reaching def" ); assert( def, "must have reaching def" );
// If input up/down sense and reg-pressure DISagree // If input up/down sense and reg-pressure DISagree
if( def->rematerialize() ) { if( def->rematerialize() ) {
def = split_Rematerialize( def, pred, pred->end_idx(), maxlrg, splits, slidx, lrg2reach, Reachblock, false ); // Place the rematerialized node above any MSCs created during
// phi node splitting. end_idx points at the insertion point
// so look at the node before it.
int insert = pred->end_idx();
while (insert >= 1 &&
pred->_nodes[insert - 1]->is_SpillCopy() &&
Find(pred->_nodes[insert - 1]) >= lrgs_before_phi_split) {
insert--;
}
def = split_Rematerialize( def, pred, insert, maxlrg, splits, slidx, lrg2reach, Reachblock, false );
if( !def ) return 0; // Bail out if( !def ) return 0; // Bail out
} }
// Update the Phi's input edge array // Update the Phi's input edge array
......
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