sparc.ad 301.8 KB
Newer Older
D
duke 已提交
1
//
2
// Copyright 1998-2009 Sun Microsystems, Inc.  All Rights Reserved.
D
duke 已提交
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This code is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License version 2 only, as
// published by the Free Software Foundation.
//
// This code is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// version 2 for more details (a copy is included in the LICENSE file that
// accompanied this code).
//
// You should have received a copy of the GNU General Public License version
// 2 along with this work; if not, write to the Free Software Foundation,
// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
//

// SPARC Architecture Description File

//----------REGISTER DEFINITION BLOCK------------------------------------------
// This information is used by the matcher and the register allocator to
// describe individual registers and classes of registers within the target
// archtecture.
register %{
//----------Architecture Description Register Definitions----------------------
// General Registers
// "reg_def"  name ( register save type, C convention save type,
//                   ideal register type, encoding, vm name );
// Register Save Types:
//
// NS  = No-Save:       The register allocator assumes that these registers
//                      can be used without saving upon entry to the method, &
//                      that they do not need to be saved at call sites.
//
// SOC = Save-On-Call:  The register allocator assumes that these registers
//                      can be used without saving upon entry to the method,
//                      but that they must be saved at call sites.
//
// SOE = Save-On-Entry: The register allocator assumes that these registers
//                      must be saved before using them upon entry to the
//                      method, but they do not need to be saved at call
//                      sites.
//
// AS  = Always-Save:   The register allocator assumes that these registers
//                      must be saved before using them upon entry to the
//                      method, & that they must be saved at call sites.
//
// Ideal Register Type is used to determine how to save & restore a
// register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
// spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
//
// The encoding number is the actual bit-pattern placed into the opcodes.


// ----------------------------
// Integer/Long Registers
// ----------------------------

// Need to expose the hi/lo aspect of 64-bit registers
// This register set is used for both the 64-bit build and
// the 32-bit build with 1-register longs.

// Global Registers 0-7
reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());

// Output Registers 0-7
reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());

// Local Registers 0-7
reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());

// Input Registers 0-7
reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());

// ----------------------------
// Float/Double Registers
// ----------------------------

// Float Registers
reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());

// Double Registers
// The rules of ADL require that double registers be defined in pairs.
// Each pair must be two 32-bit values, but not necessarily a pair of
// single float registers.  In each pair, ADLC-assigned register numbers
// must be adjacent, with the lower number even.  Finally, when the
// CPU stores such a register pair to memory, the word associated with
// the lower ADLC-assigned number must be stored to the lower address.

// These definitions specify the actual bit encodings of the sparc
// double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
// wants 0-63, so we have to convert every time we want to use fp regs
// with the macroassembler, using reg_to_DoubleFloatRegister_object().
T
twisti 已提交
192
// 255 is a flag meaning "don't go here".
D
duke 已提交
193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
// I believe we can't handle callee-save doubles D32 and up until
// the place in the sparc stack crawler that asserts on the 255 is
// fixed up.
reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg());
reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg()->next());
reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg());
reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg()->next());
reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg());
reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg()->next());
reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg());
reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg()->next());
reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg());
reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg()->next());
reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg());
reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()->next());
reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg());
reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()->next());
reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg());
reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()->next());
reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg());
reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()->next());
reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg());
reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()->next());
reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg());
reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()->next());
reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg());
reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()->next());
reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg());
reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()->next());
reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg());
reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()->next());
reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg());
reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()->next());
reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg());
reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()->next());


// ----------------------------
// Special Registers
// Condition Codes Flag Registers
// I tried to break out ICC and XCC but it's not very pretty.
// Every Sparc instruction which defs/kills one also kills the other.
// Hence every compare instruction which defs one kind of flags ends
// up needing a kill of the other.
reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());

reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());

// ----------------------------
// Specify the enum values for the registers.  These enums are only used by the
// OptoReg "class". We can convert these enum values at will to VMReg when needed
// for visibility to the rest of the vm. The order of this enum influences the
// register allocator so having the freedom to set this order and not be stuck
// with the order that is natural for the rest of the vm is worth it.
alloc_class chunk0(
  R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
  R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
  R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
  R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);

// Note that a register is not allocatable unless it is also mentioned
// in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.

alloc_class chunk1(
  // The first registers listed here are those most likely to be used
  // as temporaries.  We move F0..F7 away from the front of the list,
  // to reduce the likelihood of interferences with parameters and
  // return values.  Likewise, we avoid using F0/F1 for parameters,
  // since they are used for return values.
  // This FPU fine-tuning is worth about 1% on the SPEC geomean.
  R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
  R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
  R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
  R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
  R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
  R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
  R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
  R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);

alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);

//----------Architecture Description Register Classes--------------------------
// Several register classes are automatically defined based upon information in
// this architecture description.
// 1) reg_class inline_cache_reg           ( as defined in frame section )
// 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
//

// G0 is not included in integer class since it has special meaning.
reg_class g0_reg(R_G0);

// ----------------------------
// Integer Register Classes
// ----------------------------
// Exclusions from i_reg:
// R_G0: hardwired zero
// R_G2: reserved by HotSpot to the TLS register (invariant within Java)
// R_G6: reserved by Solaris ABI to tools
// R_G7: reserved by Solaris ABI to libthread
// R_O7: Used as a temp in many encodings
reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

// Class for all integer registers, except the G registers.  This is used for
// encodings which use G registers as temps.  The regular inputs to such
// instructions use a "notemp_" prefix, as a hack to ensure that the allocator
// will not put an input into a temp register.
reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);

reg_class g1_regI(R_G1);
reg_class g3_regI(R_G3);
reg_class g4_regI(R_G4);
reg_class o0_regI(R_O0);
reg_class o7_regI(R_O7);

// ----------------------------
// Pointer Register Classes
// ----------------------------
#ifdef _LP64
// 64-bit build means 64-bit pointers means hi/lo pairs
reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
// Lock encodings use G3 and G4 internally
reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
// Special class for storeP instructions, which can store SP or RPC to TLS.
// It is also used for memory addressing, allowing direct TLS addressing.
reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
                  R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
                  R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
                  R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
// R_L7 is the lowest-priority callee-save (i.e., NS) register
// We use it to save R_G2 across calls out of Java.
reg_class l7_regP(R_L7H,R_L7);

// Other special pointer regs
reg_class g1_regP(R_G1H,R_G1);
reg_class g2_regP(R_G2H,R_G2);
reg_class g3_regP(R_G3H,R_G3);
reg_class g4_regP(R_G4H,R_G4);
reg_class g5_regP(R_G5H,R_G5);
reg_class i0_regP(R_I0H,R_I0);
reg_class o0_regP(R_O0H,R_O0);
reg_class o1_regP(R_O1H,R_O1);
reg_class o2_regP(R_O2H,R_O2);
reg_class o7_regP(R_O7H,R_O7);

#else // _LP64
// 32-bit build means 32-bit pointers means 1 register.
reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
// Lock encodings use G3 and G4 internally
reg_class lock_ptr_reg(R_G1,               R_G5,
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
// Special class for storeP instructions, which can store SP or RPC to TLS.
// It is also used for memory addressing, allowing direct TLS addressing.
reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
                  R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
                  R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
                  R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
// R_L7 is the lowest-priority callee-save (i.e., NS) register
// We use it to save R_G2 across calls out of Java.
reg_class l7_regP(R_L7);

// Other special pointer regs
reg_class g1_regP(R_G1);
reg_class g2_regP(R_G2);
reg_class g3_regP(R_G3);
reg_class g4_regP(R_G4);
reg_class g5_regP(R_G5);
reg_class i0_regP(R_I0);
reg_class o0_regP(R_O0);
reg_class o1_regP(R_O1);
reg_class o2_regP(R_O2);
reg_class o7_regP(R_O7);
#endif // _LP64


// ----------------------------
// Long Register Classes
// ----------------------------
// Longs in 1 register.  Aligned adjacent hi/lo pairs.
// Note:  O7 is never in this class; it is sometimes used as an encoding temp.
reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
                   ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
#ifdef _LP64
// 64-bit, longs in 1 register: use all 64-bit integer registers
// 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
                   ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
                   ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
#endif // _LP64
                  );

reg_class g1_regL(R_G1H,R_G1);
398
reg_class g3_regL(R_G3H,R_G3);
D
duke 已提交
399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464
reg_class o2_regL(R_O2H,R_O2);
reg_class o7_regL(R_O7H,R_O7);

// ----------------------------
// Special Class for Condition Code Flags Register
reg_class int_flags(CCR);
reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
reg_class float_flag0(FCC0);


// ----------------------------
// Float Point Register Classes
// ----------------------------
// Skip F30/F31, they are reserved for mem-mem copies
reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);

// Paired floating point registers--they show up in the same order as the floats,
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
                   /* Use extra V9 double registers; this AD file does not support V8 */
                   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
                   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
                   );

// Paired floating point registers--they show up in the same order as the floats,
// but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
// This class is usable for mis-aligned loads as happen in I2C adapters.
reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
                   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 );
%}

//----------DEFINITION BLOCK---------------------------------------------------
// Define name --> value mappings to inform the ADLC of an integer valued name
// Current support includes integer values in the range [0, 0x7FFFFFFF]
// Format:
//        int_def  <name>         ( <int_value>, <expression>);
// Generated Code in ad_<arch>.hpp
//        #define  <name>   (<expression>)
//        // value == <int_value>
// Generated code in ad_<arch>.cpp adlc_verification()
//        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
//
definitions %{
// The default cost (of an ALU instruction).
  int_def DEFAULT_COST      (    100,     100);
  int_def HUGE_COST         (1000000, 1000000);

// Memory refs are twice as expensive as run-of-the-mill.
  int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);

// Branches are even more expensive.
  int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
  int_def CALL_COST         (    300, DEFAULT_COST * 3);
%}


//----------SOURCE BLOCK-------------------------------------------------------
// This is a block of C++ code which provides values, functions, and
// definitions necessary in the rest of the architecture description
source_hpp %{
// Must be visible to the DFA in dfa_sparc.cpp
extern bool can_branch_register( Node *bol, Node *cmp );

// Macros to extract hi & lo halves from a long pair.
// G0 is not part of any long pair, so assert on that.
T
twisti 已提交
465
// Prevents accidentally using G1 instead of G0.
D
duke 已提交
466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547
#define LONG_HI_REG(x) (x)
#define LONG_LO_REG(x) (x)

%}

source %{
#define __ _masm.

// tertiary op of a LoadP or StoreP encoding
#define REGP_OP true

static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
static Register reg_to_register_object(int register_encoding);

// Used by the DFA in dfa_sparc.cpp.
// Check for being able to use a V9 branch-on-register.  Requires a
// compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
// extended.  Doesn't work following an integer ADD, for example, because of
// overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
// replace them with zero, which could become sign-extension in a different OS
// release.  There's no obvious reason why an interrupt will ever fill these
// bits with non-zero junk (the registers are reloaded with standard LD
// instructions which either zero-fill or sign-fill).
bool can_branch_register( Node *bol, Node *cmp ) {
  if( !BranchOnRegister ) return false;
#ifdef _LP64
  if( cmp->Opcode() == Op_CmpP )
    return true;  // No problems with pointer compares
#endif
  if( cmp->Opcode() == Op_CmpL )
    return true;  // No problems with long compares

  if( !SparcV9RegsHiBitsZero ) return false;
  if( bol->as_Bool()->_test._test != BoolTest::ne &&
      bol->as_Bool()->_test._test != BoolTest::eq )
     return false;

  // Check for comparing against a 'safe' value.  Any operation which
  // clears out the high word is safe.  Thus, loads and certain shifts
  // are safe, as are non-negative constants.  Any operation which
  // preserves zero bits in the high word is safe as long as each of its
  // inputs are safe.  Thus, phis and bitwise booleans are safe if their
  // inputs are safe.  At present, the only important case to recognize
  // seems to be loads.  Constants should fold away, and shifts &
  // logicals can use the 'cc' forms.
  Node *x = cmp->in(1);
  if( x->is_Load() ) return true;
  if( x->is_Phi() ) {
    for( uint i = 1; i < x->req(); i++ )
      if( !x->in(i)->is_Load() )
        return false;
    return true;
  }
  return false;
}

// ****************************************************************************

// REQUIRED FUNCTIONALITY

// !!!!! Special hack to get all type of calls to specify the byte offset
//       from the start of the call to the point where the return address
//       will point.
//       The "return address" is the address of the call instruction, plus 8.

int MachCallStaticJavaNode::ret_addr_offset() {
  return NativeCall::instruction_size;  // call; delay slot
}

int MachCallDynamicJavaNode::ret_addr_offset() {
  int vtable_index = this->_vtable_index;
  if (vtable_index < 0) {
    // must be invalid_vtable_index, not nonvirtual_vtable_index
    assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
    return (NativeMovConstReg::instruction_size +
           NativeCall::instruction_size);  // sethi; setlo; call; delay slot
  } else {
    assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
    int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
    int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
548 549
    int klass_load_size;
    if (UseCompressedOops) {
550 551 552 553 554
      assert(Universe::heap() != NULL, "java heap should be initialized");
      if (Universe::narrow_oop_base() == NULL)
        klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass()
      else
        klass_load_size = 3*BytesPerInstWord;
555 556 557
    } else {
      klass_load_size = 1*BytesPerInstWord;
    }
D
duke 已提交
558
    if( Assembler::is_simm13(v_off) ) {
559 560
      return klass_load_size +
             (2*BytesPerInstWord +           // ld_ptr, ld_ptr
D
duke 已提交
561 562
             NativeCall::instruction_size);  // call; delay slot
    } else {
563 564
      return klass_load_size +
             (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
D
duke 已提交
565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768
             NativeCall::instruction_size);  // call; delay slot
    }
  }
}

int MachCallRuntimeNode::ret_addr_offset() {
#ifdef _LP64
  return NativeFarCall::instruction_size;  // farcall; delay slot
#else
  return NativeCall::instruction_size;  // call; delay slot
#endif
}

// Indicate if the safepoint node needs the polling page as an input.
// Since Sparc does not have absolute addressing, it does.
bool SafePointNode::needs_polling_address_input() {
  return true;
}

// emit an interrupt that is caught by the debugger (for debugging compiler)
void emit_break(CodeBuffer &cbuf) {
  MacroAssembler _masm(&cbuf);
  __ breakpoint_trap();
}

#ifndef PRODUCT
void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
  st->print("TA");
}
#endif

void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  emit_break(cbuf);
}

uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
  return MachNode::size(ra_);
}

// Traceable jump
void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
  MacroAssembler _masm(&cbuf);
  Register rdest = reg_to_register_object(jump_target);
  __ JMP(rdest, 0);
  __ delayed()->nop();
}

// Traceable jump and set exception pc
void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
  MacroAssembler _masm(&cbuf);
  Register rdest = reg_to_register_object(jump_target);
  __ JMP(rdest, 0);
  __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
}

void emit_nop(CodeBuffer &cbuf) {
  MacroAssembler _masm(&cbuf);
  __ nop();
}

void emit_illtrap(CodeBuffer &cbuf) {
  MacroAssembler _masm(&cbuf);
  __ illtrap(0);
}


intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
  assert(n->rule() != loadUB_rule, "");

  intptr_t offset = 0;
  const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
  const Node* addr = n->get_base_and_disp(offset, adr_type);
  assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
  assert(addr != NULL && addr != (Node*)-1, "invalid addr");
  assert(addr->bottom_type()->isa_oopptr() == atype, "");
  atype = atype->add_offset(offset);
  assert(disp32 == offset, "wrong disp32");
  return atype->_offset;
}


intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
  assert(n->rule() != loadUB_rule, "");

  intptr_t offset = 0;
  Node* addr = n->in(2);
  assert(addr->bottom_type()->isa_oopptr() == atype, "");
  if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
    Node* a = addr->in(2/*AddPNode::Address*/);
    Node* o = addr->in(3/*AddPNode::Offset*/);
    offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
    atype = a->bottom_type()->is_ptr()->add_offset(offset);
    assert(atype->isa_oop_ptr(), "still an oop");
  }
  offset = atype->is_ptr()->_offset;
  if (offset != Type::OffsetBot)  offset += disp32;
  return offset;
}

// Standard Sparc opcode form2 field breakdown
static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
  f0 &= (1<<19)-1;     // Mask displacement to 19 bits
  int op = (f30 << 30) |
           (f29 << 29) |
           (f25 << 25) |
           (f22 << 22) |
           (f20 << 20) |
           (f19 << 19) |
           (f0  <<  0);
  *((int*)(cbuf.code_end())) = op;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
}

// Standard Sparc opcode form2 field breakdown
static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
  f0 >>= 10;           // Drop 10 bits
  f0 &= (1<<22)-1;     // Mask displacement to 22 bits
  int op = (f30 << 30) |
           (f25 << 25) |
           (f22 << 22) |
           (f0  <<  0);
  *((int*)(cbuf.code_end())) = op;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
}

// Standard Sparc opcode form3 field breakdown
static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
  int op = (f30 << 30) |
           (f25 << 25) |
           (f19 << 19) |
           (f14 << 14) |
           (f5  <<  5) |
           (f0  <<  0);
  *((int*)(cbuf.code_end())) = op;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
}

// Standard Sparc opcode form3 field breakdown
static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
  simm13 &= (1<<13)-1; // Mask to 13 bits
  int op = (f30 << 30) |
           (f25 << 25) |
           (f19 << 19) |
           (f14 << 14) |
           (1   << 13) | // bit to indicate immediate-mode
           (simm13<<0);
  *((int*)(cbuf.code_end())) = op;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
}

static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
  simm10 &= (1<<10)-1; // Mask to 10 bits
  emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
}

#ifdef ASSERT
// Helper function for VerifyOops in emit_form3_mem_reg
void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
  warning("VerifyOops encountered unexpected instruction:");
  n->dump(2);
  warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
}
#endif


void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
                        int src1_enc, int disp32, int src2_enc, int dst_enc) {

#ifdef ASSERT
  // The following code implements the +VerifyOops feature.
  // It verifies oop values which are loaded into or stored out of
  // the current method activation.  +VerifyOops complements techniques
  // like ScavengeALot, because it eagerly inspects oops in transit,
  // as they enter or leave the stack, as opposed to ScavengeALot,
  // which inspects oops "at rest", in the stack or heap, at safepoints.
  // For this reason, +VerifyOops can sometimes detect bugs very close
  // to their point of creation.  It can also serve as a cross-check
  // on the validity of oop maps, when used toegether with ScavengeALot.

  // It would be good to verify oops at other points, especially
  // when an oop is used as a base pointer for a load or store.
  // This is presently difficult, because it is hard to know when
  // a base address is biased or not.  (If we had such information,
  // it would be easy and useful to make a two-argument version of
  // verify_oop which unbiases the base, and performs verification.)

  assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
  bool is_verified_oop_base  = false;
  bool is_verified_oop_load  = false;
  bool is_verified_oop_store = false;
  int tmp_enc = -1;
  if (VerifyOops && src1_enc != R_SP_enc) {
    // classify the op, mainly for an assert check
    int st_op = 0, ld_op = 0;
    switch (primary) {
    case Assembler::stb_op3:  st_op = Op_StoreB; break;
    case Assembler::sth_op3:  st_op = Op_StoreC; break;
    case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
    case Assembler::stw_op3:  st_op = Op_StoreI; break;
    case Assembler::std_op3:  st_op = Op_StoreL; break;
    case Assembler::stf_op3:  st_op = Op_StoreF; break;
    case Assembler::stdf_op3: st_op = Op_StoreD; break;

    case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
769
    case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
D
duke 已提交
770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982
    case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
    case Assembler::ldx_op3:  // may become LoadP or stay LoadI
    case Assembler::ldsw_op3: // may become LoadP or stay LoadI
    case Assembler::lduw_op3: ld_op = Op_LoadI; break;
    case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
    case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
    case Assembler::lddf_op3: ld_op = Op_LoadD; break;
    case Assembler::ldub_op3: ld_op = Op_LoadB; break;
    case Assembler::prefetch_op3: ld_op = Op_LoadI; break;

    default: ShouldNotReachHere();
    }
    if (tertiary == REGP_OP) {
      if      (st_op == Op_StoreI)  st_op = Op_StoreP;
      else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
      else                          ShouldNotReachHere();
      if (st_op) {
        // a store
        // inputs are (0:control, 1:memory, 2:address, 3:value)
        Node* n2 = n->in(3);
        if (n2 != NULL) {
          const Type* t = n2->bottom_type();
          is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
        }
      } else {
        // a load
        const Type* t = n->bottom_type();
        is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
      }
    }

    if (ld_op) {
      // a Load
      // inputs are (0:control, 1:memory, 2:address)
      if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
          !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
          !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
          !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
          !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
          !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
          !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
          !(n->ideal_Opcode()==Op_PrefetchRead  && ld_op==Op_LoadI) &&
          !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) &&
          !(n->rule() == loadUB_rule)) {
        verify_oops_warning(n, n->ideal_Opcode(), ld_op);
      }
    } else if (st_op) {
      // a Store
      // inputs are (0:control, 1:memory, 2:address, 3:value)
      if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
          !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
          !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
          !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
          !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
          !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
        verify_oops_warning(n, n->ideal_Opcode(), st_op);
      }
    }

    if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
      Node* addr = n->in(2);
      if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
        const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
        if (atype != NULL) {
          intptr_t offset = get_offset_from_base(n, atype, disp32);
          intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
          if (offset != offset_2) {
            get_offset_from_base(n, atype, disp32);
            get_offset_from_base_2(n, atype, disp32);
          }
          assert(offset == offset_2, "different offsets");
          if (offset == disp32) {
            // we now know that src1 is a true oop pointer
            is_verified_oop_base = true;
            if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
              if( primary == Assembler::ldd_op3 ) {
                is_verified_oop_base = false; // Cannot 'ldd' into O7
              } else {
                tmp_enc = dst_enc;
                dst_enc = R_O7_enc; // Load into O7; preserve source oop
                assert(src1_enc != dst_enc, "");
              }
            }
          }
          if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
                       || offset == oopDesc::mark_offset_in_bytes())) {
                      // loading the mark should not be allowed either, but
                      // we don't check this since it conflicts with InlineObjectHash
                      // usage of LoadINode to get the mark. We could keep the
                      // check if we create a new LoadMarkNode
            // but do not verify the object before its header is initialized
            ShouldNotReachHere();
          }
        }
      }
    }
  }
#endif

  uint instr;
  instr = (Assembler::ldst_op << 30)
        | (dst_enc        << 25)
        | (primary        << 19)
        | (src1_enc       << 14);

  uint index = src2_enc;
  int disp = disp32;

  if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
    disp += STACK_BIAS;

  // We should have a compiler bailout here rather than a guarantee.
  // Better yet would be some mechanism to handle variable-size matches correctly.
  guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );

  if( disp == 0 ) {
    // use reg-reg form
    // bit 13 is already zero
    instr |= index;
  } else {
    // use reg-imm form
    instr |= 0x00002000;          // set bit 13 to one
    instr |= disp & 0x1FFF;
  }

  uint *code = (uint*)cbuf.code_end();
  *code = instr;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);

#ifdef ASSERT
  {
    MacroAssembler _masm(&cbuf);
    if (is_verified_oop_base) {
      __ verify_oop(reg_to_register_object(src1_enc));
    }
    if (is_verified_oop_store) {
      __ verify_oop(reg_to_register_object(dst_enc));
    }
    if (tmp_enc != -1) {
      __ mov(O7, reg_to_register_object(tmp_enc));
    }
    if (is_verified_oop_load) {
      __ verify_oop(reg_to_register_object(dst_enc));
    }
  }
#endif
}

void emit_form3_mem_reg_asi(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary,
                        int src1_enc, int disp32, int src2_enc, int dst_enc, int asi) {

  uint instr;
  instr = (Assembler::ldst_op << 30)
        | (dst_enc        << 25)
        | (primary        << 19)
        | (src1_enc       << 14);

  int disp = disp32;
  int index    = src2_enc;

  if (src1_enc == R_SP_enc || src1_enc == R_FP_enc)
    disp += STACK_BIAS;

  // We should have a compiler bailout here rather than a guarantee.
  // Better yet would be some mechanism to handle variable-size matches correctly.
  guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );

  if( disp != 0 ) {
    // use reg-reg form
    // set src2=R_O7 contains offset
    index = R_O7_enc;
    emit3_simm13( cbuf, Assembler::arith_op, index, Assembler::or_op3, 0, disp);
  }
  instr |= (asi << 5);
  instr |= index;
  uint *code = (uint*)cbuf.code_end();
  *code = instr;
  cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
}

void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) {
  // The method which records debug information at every safepoint
  // expects the call to be the first instruction in the snippet as
  // it creates a PcDesc structure which tracks the offset of a call
  // from the start of the codeBlob. This offset is computed as
  // code_end() - code_begin() of the code which has been emitted
  // so far.
  // In this particular case we have skirted around the problem by
  // putting the "mov" instruction in the delay slot but the problem
  // may bite us again at some other point and a cleaner/generic
  // solution using relocations would be needed.
  MacroAssembler _masm(&cbuf);
  __ set_inst_mark();

  // We flush the current window just so that there is a valid stack copy
  // the fact that the current window becomes active again instantly is
  // not a problem there is nothing live in it.

#ifdef ASSERT
  int startpos = __ offset();
#endif /* ASSERT */

#ifdef _LP64
  // Calls to the runtime or native may not be reachable from compiled code,
  // so we generate the far call sequence on 64 bit sparc.
  // This code sequence is relocatable to any address, even on LP64.
  if ( force_far_call ) {
    __ relocate(rtype);
983 984
    AddressLiteral dest(entry_point);
    __ jumpl_to(dest, O7, O7);
D
duke 已提交
985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140
  }
  else
#endif
  {
     __ call((address)entry_point, rtype);
  }

  if (preserve_g2)   __ delayed()->mov(G2, L7);
  else __ delayed()->nop();

  if (preserve_g2)   __ mov(L7, G2);

#ifdef ASSERT
  if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
#ifdef _LP64
    // Trash argument dump slots.
    __ set(0xb0b8ac0db0b8ac0d, G1);
    __ mov(G1, G5);
    __ stx(G1, SP, STACK_BIAS + 0x80);
    __ stx(G1, SP, STACK_BIAS + 0x88);
    __ stx(G1, SP, STACK_BIAS + 0x90);
    __ stx(G1, SP, STACK_BIAS + 0x98);
    __ stx(G1, SP, STACK_BIAS + 0xA0);
    __ stx(G1, SP, STACK_BIAS + 0xA8);
#else // _LP64
    // this is also a native call, so smash the first 7 stack locations,
    // and the various registers

    // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
    // while [SP+0x44..0x58] are the argument dump slots.
    __ set((intptr_t)0xbaadf00d, G1);
    __ mov(G1, G5);
    __ sllx(G1, 32, G1);
    __ or3(G1, G5, G1);
    __ mov(G1, G5);
    __ stx(G1, SP, 0x40);
    __ stx(G1, SP, 0x48);
    __ stx(G1, SP, 0x50);
    __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
#endif // _LP64
  }
#endif /*ASSERT*/
}

//=============================================================================
// REQUIRED FUNCTIONALITY for encoding
void emit_lo(CodeBuffer &cbuf, int val) {  }
void emit_hi(CodeBuffer &cbuf, int val) {  }


//=============================================================================

#ifndef PRODUCT
void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
  Compile* C = ra_->C;

  for (int i = 0; i < OptoPrologueNops; i++) {
    st->print_cr("NOP"); st->print("\t");
  }

  if( VerifyThread ) {
    st->print_cr("Verify_Thread"); st->print("\t");
  }

  size_t framesize = C->frame_slots() << LogBytesPerInt;

  // Calls to C2R adapters often do not accept exceptional returns.
  // We require that their callers must bang for them.  But be careful, because
  // some VM calls (such as call site linkage) can use several kilobytes of
  // stack.  But the stack safety zone should account for that.
  // See bugs 4446381, 4468289, 4497237.
  if (C->need_stack_bang(framesize)) {
    st->print_cr("! stack bang"); st->print("\t");
  }

  if (Assembler::is_simm13(-framesize)) {
    st->print   ("SAVE   R_SP,-%d,R_SP",framesize);
  } else {
    st->print_cr("SETHI  R_SP,hi%%(-%d),R_G3",framesize); st->print("\t");
    st->print_cr("ADD    R_G3,lo%%(-%d),R_G3",framesize); st->print("\t");
    st->print   ("SAVE   R_SP,R_G3,R_SP");
  }

}
#endif

void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  Compile* C = ra_->C;
  MacroAssembler _masm(&cbuf);

  for (int i = 0; i < OptoPrologueNops; i++) {
    __ nop();
  }

  __ verify_thread();

  size_t framesize = C->frame_slots() << LogBytesPerInt;
  assert(framesize >= 16*wordSize, "must have room for reg. save area");
  assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");

  // Calls to C2R adapters often do not accept exceptional returns.
  // We require that their callers must bang for them.  But be careful, because
  // some VM calls (such as call site linkage) can use several kilobytes of
  // stack.  But the stack safety zone should account for that.
  // See bugs 4446381, 4468289, 4497237.
  if (C->need_stack_bang(framesize)) {
    __ generate_stack_overflow_check(framesize);
  }

  if (Assembler::is_simm13(-framesize)) {
    __ save(SP, -framesize, SP);
  } else {
    __ sethi(-framesize & ~0x3ff, G3);
    __ add(G3, -framesize & 0x3ff, G3);
    __ save(SP, G3, SP);
  }
  C->set_frame_complete( __ offset() );
}

uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
  return MachNode::size(ra_);
}

int MachPrologNode::reloc() const {
  return 10; // a large enough number
}

//=============================================================================
#ifndef PRODUCT
void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
  Compile* C = ra_->C;

  if( do_polling() && ra_->C->is_method_compilation() ) {
    st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
#ifdef _LP64
    st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
#else
    st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
#endif
  }

  if( do_polling() )
    st->print("RET\n\t");

  st->print("RESTORE");
}
#endif

void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  MacroAssembler _masm(&cbuf);
  Compile* C = ra_->C;

  __ verify_thread();

  // If this does safepoint polling, then do it here
  if( do_polling() && ra_->C->is_method_compilation() ) {
1141 1142
    AddressLiteral polling_page(os::get_polling_page());
    __ sethi(polling_page, L0);
D
duke 已提交
1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426
    __ relocate(relocInfo::poll_return_type);
    __ ld_ptr( L0, 0, G0 );
  }

  // If this is a return, then stuff the restore in the delay slot
  if( do_polling() ) {
    __ ret();
    __ delayed()->restore();
  } else {
    __ restore();
  }
}

uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
  return MachNode::size(ra_);
}

int MachEpilogNode::reloc() const {
  return 16; // a large enough number
}

const Pipeline * MachEpilogNode::pipeline() const {
  return MachNode::pipeline_class();
}

int MachEpilogNode::safepoint_offset() const {
  assert( do_polling(), "no return for this epilog node");
  return MacroAssembler::size_of_sethi(os::get_polling_page());
}

//=============================================================================

// Figure out which register class each belongs in: rc_int, rc_float, rc_stack
enum RC { rc_bad, rc_int, rc_float, rc_stack };
static enum RC rc_class( OptoReg::Name reg ) {
  if( !OptoReg::is_valid(reg)  ) return rc_bad;
  if (OptoReg::is_stack(reg)) return rc_stack;
  VMReg r = OptoReg::as_VMReg(reg);
  if (r->is_Register()) return rc_int;
  assert(r->is_FloatRegister(), "must be");
  return rc_float;
}

static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
  if( cbuf ) {
    // Better yet would be some mechanism to handle variable-size matches correctly
    if (!Assembler::is_simm13(offset + STACK_BIAS)) {
      ra_->C->record_method_not_compilable("unable to handle large constant offsets");
    } else {
      emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
    }
  }
#ifndef PRODUCT
  else if( !do_size ) {
    if( size != 0 ) st->print("\n\t");
    if( is_load ) st->print("%s   [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
    else          st->print("%s   R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
  }
#endif
  return size+4;
}

static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
  if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
#ifndef PRODUCT
  else if( !do_size ) {
    if( size != 0 ) st->print("\n\t");
    st->print("%s  R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
  }
#endif
  return size+4;
}

uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
                                        PhaseRegAlloc *ra_,
                                        bool do_size,
                                        outputStream* st ) const {
  // Get registers to move
  OptoReg::Name src_second = ra_->get_reg_second(in(1));
  OptoReg::Name src_first = ra_->get_reg_first(in(1));
  OptoReg::Name dst_second = ra_->get_reg_second(this );
  OptoReg::Name dst_first = ra_->get_reg_first(this );

  enum RC src_second_rc = rc_class(src_second);
  enum RC src_first_rc = rc_class(src_first);
  enum RC dst_second_rc = rc_class(dst_second);
  enum RC dst_first_rc = rc_class(dst_first);

  assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );

  // Generate spill code!
  int size = 0;

  if( src_first == dst_first && src_second == dst_second )
    return size;            // Self copy, no move

  // --------------------------------------
  // Check for mem-mem move.  Load into unused float registers and fall into
  // the float-store case.
  if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
    int offset = ra_->reg2offset(src_first);
    // Further check for aligned-adjacent pair, so we can use a double load
    if( (src_first&1)==0 && src_first+1 == src_second ) {
      src_second    = OptoReg::Name(R_F31_num);
      src_second_rc = rc_float;
      size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
    } else {
      size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
    }
    src_first    = OptoReg::Name(R_F30_num);
    src_first_rc = rc_float;
  }

  if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
    int offset = ra_->reg2offset(src_second);
    size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
    src_second    = OptoReg::Name(R_F31_num);
    src_second_rc = rc_float;
  }

  // --------------------------------------
  // Check for float->int copy; requires a trip through memory
  if( src_first_rc == rc_float && dst_first_rc == rc_int ) {
    int offset = frame::register_save_words*wordSize;
    if( cbuf ) {
      emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
      impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
      impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
      emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
    }
#ifndef PRODUCT
    else if( !do_size ) {
      if( size != 0 ) st->print("\n\t");
      st->print(  "SUB    R_SP,16,R_SP\n");
      impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
      impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
      st->print("\tADD    R_SP,16,R_SP\n");
    }
#endif
    size += 16;
  }

  // --------------------------------------
  // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
  // In such cases, I have to do the big-endian swap.  For aligned targets, the
  // hardware does the flop for me.  Doubles are always aligned, so no problem
  // there.  Misaligned sources only come from native-long-returns (handled
  // special below).
#ifndef _LP64
  if( src_first_rc == rc_int &&     // source is already big-endian
      src_second_rc != rc_bad &&    // 64-bit move
      ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
    assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
    // Do the big-endian flop.
    OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
    enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
  }
#endif

  // --------------------------------------
  // Check for integer reg-reg copy
  if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
#ifndef _LP64
    if( src_first == R_O0_num && src_second == R_O1_num ) {  // Check for the evil O0/O1 native long-return case
      // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
      //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
      //       operand contains the least significant word of the 64-bit value and vice versa.
      OptoReg::Name tmp = OptoReg::Name(R_O7_num);
      assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
      // Shift O0 left in-place, zero-extend O1, then OR them into the dst
      if( cbuf ) {
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
        emit3       ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
#ifndef PRODUCT
      } else if( !do_size ) {
        if( size != 0 ) st->print("\n\t");
        st->print("SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
        st->print("SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
        st->print("OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
#endif
      }
      return size+12;
    }
    else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
      // returning a long value in I0/I1
      // a SpillCopy must be able to target a return instruction's reg_class
      // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
      //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
      //       operand contains the least significant word of the 64-bit value and vice versa.
      OptoReg::Name tdest = dst_first;

      if (src_first == dst_first) {
        tdest = OptoReg::Name(R_O7_num);
        size += 4;
      }

      if( cbuf ) {
        assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
        // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
        // ShrL_reg_imm6
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
        // ShrR_reg_imm6  src, 0, dst
        emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
        if (tdest != dst_first) {
          emit3     ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
        }
      }
#ifndef PRODUCT
      else if( !do_size ) {
        if( size != 0 ) st->print("\n\t");  // %%%%% !!!!!
        st->print("SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
        st->print("SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
        if (tdest != dst_first) {
          st->print("MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
        }
      }
#endif // PRODUCT
      return size+8;
    }
#endif // !_LP64
    // Else normal reg-reg copy
    assert( src_second != dst_first, "smashed second before evacuating it" );
    size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV  ",size, st);
    assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
    // This moves an aligned adjacent pair.
    // See if we are done.
    if( src_first+1 == src_second && dst_first+1 == dst_second )
      return size;
  }

  // Check for integer store
  if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
    int offset = ra_->reg2offset(dst_first);
    // Further check for aligned-adjacent pair, so we can use a double store
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
      return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
    size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
  }

  // Check for integer load
  if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
    int offset = ra_->reg2offset(src_first);
    // Further check for aligned-adjacent pair, so we can use a double load
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
      return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
    size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
  }

  // Check for float reg-reg copy
  if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
    // Further check for aligned-adjacent pair, so we can use a double move
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
      return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
    size  =  impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
  }

  // Check for float store
  if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
    int offset = ra_->reg2offset(dst_first);
    // Further check for aligned-adjacent pair, so we can use a double store
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
      return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
    size  =  impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
  }

  // Check for float load
  if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
    int offset = ra_->reg2offset(src_first);
    // Further check for aligned-adjacent pair, so we can use a double load
    if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
      return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
    size  =  impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
  }

  // --------------------------------------------------------------------
  // Check for hi bits still needing moving.  Only happens for misaligned
  // arguments to native calls.
  if( src_second == dst_second )
    return size;               // Self copy; no move
  assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );

#ifndef _LP64
  // In the LP64 build, all registers can be moved as aligned/adjacent
T
twisti 已提交
1427
  // pairs, so there's never any need to move the high bits separately.
D
duke 已提交
1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567
  // The 32-bit builds have to deal with the 32-bit ABI which can force
  // all sorts of silly alignment problems.

  // Check for integer reg-reg copy.  Hi bits are stuck up in the top
  // 32-bits of a 64-bit register, but are needed in low bits of another
  // register (else it's a hi-bits-to-hi-bits copy which should have
  // happened already as part of a 64-bit move)
  if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
    assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
    assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
    // Shift src_second down to dst_second's low bits.
    if( cbuf ) {
      emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
#ifndef PRODUCT
    } else if( !do_size ) {
      if( size != 0 ) st->print("\n\t");
      st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
#endif
    }
    return size+4;
  }

  // Check for high word integer store.  Must down-shift the hi bits
  // into a temp register, then fall into the case of storing int bits.
  if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
    // Shift src_second down to dst_second's low bits.
    if( cbuf ) {
      emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
#ifndef PRODUCT
    } else if( !do_size ) {
      if( size != 0 ) st->print("\n\t");
      st->print("SRLX   R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
#endif
    }
    size+=4;
    src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
  }

  // Check for high word integer load
  if( dst_second_rc == rc_int && src_second_rc == rc_stack )
    return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);

  // Check for high word integer store
  if( src_second_rc == rc_int && dst_second_rc == rc_stack )
    return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);

  // Check for high word float store
  if( src_second_rc == rc_float && dst_second_rc == rc_stack )
    return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);

#endif // !_LP64

  Unimplemented();
}

#ifndef PRODUCT
void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
  implementation( NULL, ra_, false, st );
}
#endif

void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  implementation( &cbuf, ra_, false, NULL );
}

uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
  return implementation( NULL, ra_, true, NULL );
}

//=============================================================================
#ifndef PRODUCT
void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
  st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
}
#endif

void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
  MacroAssembler _masm(&cbuf);
  for(int i = 0; i < _count; i += 1) {
    __ nop();
  }
}

uint MachNopNode::size(PhaseRegAlloc *ra_) const {
  return 4 * _count;
}


//=============================================================================
#ifndef PRODUCT
void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
  int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
  int reg = ra_->get_reg_first(this);
  st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
}
#endif

void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  MacroAssembler _masm(&cbuf);
  int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
  int reg = ra_->get_encode(this);

  if (Assembler::is_simm13(offset)) {
     __ add(SP, offset, reg_to_register_object(reg));
  } else {
     __ set(offset, O7);
     __ add(SP, O7, reg_to_register_object(reg));
  }
}

uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
  // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
  assert(ra_ == ra_->C->regalloc(), "sanity");
  return ra_->C->scratch_emit_size(this);
}

//=============================================================================

// emit call stub, compiled java to interpretor
void emit_java_to_interp(CodeBuffer &cbuf ) {

  // Stub is fixed up when the corresponding call is converted from calling
  // compiled code to calling interpreted code.
  // set (empty), G5
  // jmp -1

  address mark = cbuf.inst_mark();  // get mark within main instrs section

  MacroAssembler _masm(&cbuf);

  address base =
  __ start_a_stub(Compile::MAX_stubs_size);
  if (base == NULL)  return;  // CodeBuffer::expand failed

  // static stub relocation stores the instruction address of the call
  __ relocate(static_stub_Relocation::spec(mark));

  __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode()));

  __ set_inst_mark();
1568 1569
  AddressLiteral addrlit(-1);
  __ JUMP(addrlit, G3, 0);
D
duke 已提交
1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595

  __ delayed()->nop();

  // Update current stubs pointer and restore code_end.
  __ end_a_stub();
}

// size of call stub, compiled java to interpretor
uint size_java_to_interp() {
  // This doesn't need to be accurate but it must be larger or equal to
  // the real size of the stub.
  return (NativeMovConstReg::instruction_size +  // sethi/setlo;
          NativeJump::instruction_size + // sethi; jmp; nop
          (TraceJumps ? 20 * BytesPerInstWord : 0) );
}
// relocation entries for call stub, compiled java to interpretor
uint reloc_java_to_interp() {
  return 10;  // 4 in emit_java_to_interp + 1 in Java_Static_Call
}


//=============================================================================
#ifndef PRODUCT
void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
  st->print_cr("\nUEP:");
#ifdef    _LP64
1596
  if (UseCompressedOops) {
1597
    assert(Universe::heap() != NULL, "java heap should be initialized");
1598 1599
    st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
    st->print_cr("\tSLL    R_G5,3,R_G5");
1600 1601
    if (Universe::narrow_oop_base() != NULL)
      st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1602 1603 1604
  } else {
    st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
  }
D
duke 已提交
1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621
  st->print_cr("\tCMP    R_G5,R_G3" );
  st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
#else  // _LP64
  st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
  st->print_cr("\tCMP    R_G5,R_G3" );
  st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
#endif // _LP64
}
#endif

void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  MacroAssembler _masm(&cbuf);
  Label L;
  Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
  Register temp_reg   = G3;
  assert( G5_ic_reg != temp_reg, "conflicting registers" );

T
twisti 已提交
1622
  // Load klass from receiver
1623
  __ load_klass(O0, temp_reg);
D
duke 已提交
1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
  // Compare against expected klass
  __ cmp(temp_reg, G5_ic_reg);
  // Branch to miss code, checks xcc or icc depending
  __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
}

uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
  return MachNode::size(ra_);
}


//=============================================================================

uint size_exception_handler() {
  if (TraceJumps) {
    return (400); // just a guess
  }
  return ( NativeJump::instruction_size ); // sethi;jmp;nop
}

uint size_deopt_handler() {
  if (TraceJumps) {
    return (400); // just a guess
  }
  return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
}

// Emit exception handler code.
int emit_exception_handler(CodeBuffer& cbuf) {
  Register temp_reg = G3;
1654
  AddressLiteral exception_blob(OptoRuntime::exception_blob()->instructions_begin());
D
duke 已提交
1655 1656 1657 1658 1659 1660 1661 1662
  MacroAssembler _masm(&cbuf);

  address base =
  __ start_a_stub(size_exception_handler());
  if (base == NULL)  return 0;  // CodeBuffer::expand failed

  int offset = __ offset();

1663
  __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
D
duke 已提交
1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
  __ delayed()->nop();

  assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");

  __ end_a_stub();

  return offset;
}

int emit_deopt_handler(CodeBuffer& cbuf) {
  // Can't use any of the current frame's registers as we may have deopted
  // at a poll and everything (including G3) can be live.
  Register temp_reg = L0;
1677
  AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
D
duke 已提交
1678 1679 1680 1681 1682 1683 1684 1685
  MacroAssembler _masm(&cbuf);

  address base =
  __ start_a_stub(size_deopt_handler());
  if (base == NULL)  return 0;  // CodeBuffer::expand failed

  int offset = __ offset();
  __ save_frame(0);
1686
  __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
D
duke 已提交
1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714
  __ delayed()->restore();

  assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");

  __ end_a_stub();
  return offset;

}

// Given a register encoding, produce a Integer Register object
static Register reg_to_register_object(int register_encoding) {
  assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
  return as_Register(register_encoding);
}

// Given a register encoding, produce a single-precision Float Register object
static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
  assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
  return as_SingleFloatRegister(register_encoding);
}

// Given a register encoding, produce a double-precision Float Register object
static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
  assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
  assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
  return as_DoubleFloatRegister(register_encoding);
}

1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731
const bool Matcher::match_rule_supported(int opcode) {
  if (!has_match_rule(opcode))
    return false;

  switch (opcode) {
  case Op_CountLeadingZerosI:
  case Op_CountLeadingZerosL:
  case Op_CountTrailingZerosI:
  case Op_CountTrailingZerosL:
    if (!UsePopCountInstruction)
      return false;
    break;
  }

  return true;  // Per default match rules are supported.
}

D
duke 已提交
1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758
int Matcher::regnum_to_fpu_offset(int regnum) {
  return regnum - 32; // The FP registers are in the second chunk
}

#ifdef ASSERT
address last_rethrow = NULL;  // debugging aid for Rethrow encoding
#endif

// Vector width in bytes
const uint Matcher::vector_width_in_bytes(void) {
  return 8;
}

// Vector ideal reg
const uint Matcher::vector_ideal_reg(void) {
  return Op_RegD;
}

// USII supports fxtof through the whole range of number, USIII doesn't
const bool Matcher::convL2FSupported(void) {
  return VM_Version::has_fast_fxtof();
}

// Is this branch offset short enough that a short branch can be used?
//
// NOTE: If the platform does not provide any short branch variants, then
//       this method should return false for offset 0.
1759
bool Matcher::is_short_branch_offset(int rule, int offset) {
D
duke 已提交
1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840
  return false;
}

const bool Matcher::isSimpleConstant64(jlong value) {
  // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
  // Depends on optimizations in MacroAssembler::setx.
  int hi = (int)(value >> 32);
  int lo = (int)(value & ~0);
  return (hi == 0) || (hi == -1) || (lo == 0);
}

// No scaling for the parameter the ClearArray node.
const bool Matcher::init_array_count_is_in_bytes = true;

// Threshold size for cleararray.
const int Matcher::init_array_short_size = 8 * BytesPerLong;

// Should the Matcher clone shifts on addressing modes, expecting them to
// be subsumed into complex addressing expressions or compute them into
// registers?  True for Intel but false for most RISCs
const bool Matcher::clone_shift_expressions = false;

// Is it better to copy float constants, or load them directly from memory?
// Intel can load a float constant from a direct address, requiring no
// extra registers.  Most RISCs will have to materialize an address into a
// register first, so they would do better to copy the constant from stack.
const bool Matcher::rematerialize_float_constants = false;

// If CPU can load and store mis-aligned doubles directly then no fixup is
// needed.  Else we split the double into 2 integer pieces and move it
// piece-by-piece.  Only happens when passing doubles into C code as the
// Java calling convention forces doubles to be aligned.
#ifdef _LP64
const bool Matcher::misaligned_doubles_ok = true;
#else
const bool Matcher::misaligned_doubles_ok = false;
#endif

// No-op on SPARC.
void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
}

// Advertise here if the CPU requires explicit rounding operations
// to implement the UseStrictFP mode.
const bool Matcher::strict_fp_requires_explicit_rounding = false;

// Do floats take an entire double register or just half?
const bool Matcher::float_in_double = false;

// Do ints take an entire long register or just half?
// Note that we if-def off of _LP64.
// The relevant question is how the int is callee-saved.  In _LP64
// the whole long is written but de-opt'ing will have to extract
// the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
#ifdef _LP64
const bool Matcher::int_in_long = true;
#else
const bool Matcher::int_in_long = false;
#endif

// Return whether or not this register is ever used as an argument.  This
// function is used on startup to build the trampoline stubs in generateOptoStub.
// Registers not mentioned will be killed by the VM call in the trampoline, and
// arguments in those registers not be available to the callee.
bool Matcher::can_be_java_arg( int reg ) {
  // Standard sparc 6 args in registers
  if( reg == R_I0_num ||
      reg == R_I1_num ||
      reg == R_I2_num ||
      reg == R_I3_num ||
      reg == R_I4_num ||
      reg == R_I5_num ) return true;
#ifdef _LP64
  // 64-bit builds can pass 64-bit pointers and longs in
  // the high I registers
  if( reg == R_I0H_num ||
      reg == R_I1H_num ||
      reg == R_I2H_num ||
      reg == R_I3H_num ||
      reg == R_I4H_num ||
      reg == R_I5H_num ) return true;
1841 1842 1843 1844 1845

  if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
    return true;
  }

D
duke 已提交
1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941
#else
  // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
  // Longs cannot be passed in O regs, because O regs become I regs
  // after a 'save' and I regs get their high bits chopped off on
  // interrupt.
  if( reg == R_G1H_num || reg == R_G1_num ) return true;
  if( reg == R_G4H_num || reg == R_G4_num ) return true;
#endif
  // A few float args in registers
  if( reg >= R_F0_num && reg <= R_F7_num ) return true;

  return false;
}

bool Matcher::is_spillable_arg( int reg ) {
  return can_be_java_arg(reg);
}

// Register for DIVI projection of divmodI
RegMask Matcher::divI_proj_mask() {
  ShouldNotReachHere();
  return RegMask();
}

// Register for MODI projection of divmodI
RegMask Matcher::modI_proj_mask() {
  ShouldNotReachHere();
  return RegMask();
}

// Register for DIVL projection of divmodL
RegMask Matcher::divL_proj_mask() {
  ShouldNotReachHere();
  return RegMask();
}

// Register for MODL projection of divmodL
RegMask Matcher::modL_proj_mask() {
  ShouldNotReachHere();
  return RegMask();
}

%}


// The intptr_t operand types, defined by textual substitution.
// (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
#ifdef _LP64
#define immX    immL
#define immX13  immL13
#define iRegX   iRegL
#define g1RegX  g1RegL
#else
#define immX    immI
#define immX13  immI13
#define iRegX   iRegI
#define g1RegX  g1RegI
#endif

//----------ENCODING BLOCK-----------------------------------------------------
// This block specifies the encoding classes used by the compiler to output
// byte streams.  Encoding classes are parameterized macros used by
// Machine Instruction Nodes in order to generate the bit encoding of the
// instruction.  Operands specify their base encoding interface with the
// interface keyword.  There are currently supported four interfaces,
// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
// operand to generate a function which returns its register number when
// queried.   CONST_INTER causes an operand to generate a function which
// returns the value of the constant when queried.  MEMORY_INTER causes an
// operand to generate four functions which return the Base Register, the
// Index Register, the Scale Value, and the Offset Value of the operand when
// queried.  COND_INTER causes an operand to generate six functions which
// return the encoding code (ie - encoding bits for the instruction)
// associated with each basic boolean condition for a conditional instruction.
//
// Instructions specify two basic values for encoding.  Again, a function
// is available to check if the constant displacement is an oop. They use the
// ins_encode keyword to specify their encoding classes (which must be
// a sequence of enc_class names, and their parameters, specified in
// the encoding block), and they use the
// opcode keyword to specify, in order, their primary, secondary, and
// tertiary opcode.  Only the opcode sections which a particular instruction
// needs for encoding need to be specified.
encode %{
  enc_class enc_untested %{
#ifdef ASSERT
    MacroAssembler _masm(&cbuf);
    __ untested("encoding");
#endif
  %}

  enc_class form3_mem_reg( memory mem, iRegI dst ) %{
    emit_form3_mem_reg(cbuf, this, $primary, $tertiary,
                       $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
  %}

1942 1943 1944 1945 1946
  enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
    emit_form3_mem_reg(cbuf, this, $primary, -1,
                       $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
  %}

D
duke 已提交
1947
  enc_class form3_mem_reg_little( memory mem, iRegI dst) %{
1948
    emit_form3_mem_reg_asi(cbuf, this, $primary, -1,
D
duke 已提交
1949 1950 1951 1952
                     $mem$$base, $mem$$disp, $mem$$index, $dst$$reg, Assembler::ASI_PRIMARY_LITTLE);
  %}

  enc_class form3_mem_prefetch_read( memory mem ) %{
1953
    emit_form3_mem_reg(cbuf, this, $primary, -1,
D
duke 已提交
1954 1955 1956 1957
                       $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
  %}

  enc_class form3_mem_prefetch_write( memory mem ) %{
1958
    emit_form3_mem_reg(cbuf, this, $primary, -1,
D
duke 已提交
1959 1960 1961 1962 1963 1964 1965
                       $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
  %}

  enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
    assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
    assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
    guarantee($mem$$index == R_G0_enc, "double index?");
1966 1967
    emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
    emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
D
duke 已提交
1968 1969 1970 1971 1972 1973 1974 1975 1976
    emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
    emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
  %}

  enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
    assert( Assembler::is_simm13($mem$$disp  ), "need disp and disp+4" );
    assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" );
    guarantee($mem$$index == R_G0_enc, "double index?");
    // Load long with 2 instructions
1977 1978
    emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
    emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
D
duke 已提交
1979 1980 1981 1982 1983
  %}

  //%%% form3_mem_plus_4_reg is a hack--get rid of it
  enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
    guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
1984
    emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
D
duke 已提交
1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269
  %}

  enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
    if( $rs2$$reg != $rd$$reg )
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
  %}

  // Target lo half of long
  enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
    if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
      emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
  %}

  // Source lo half of long
  enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
    if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
  %}

  // Target hi half of long
  enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
  %}

  // Source lo half of long, and leave it sign extended.
  enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
    // Sign extend low half
    emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
  %}

  // Source hi half of long, and leave it sign extended.
  enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
    // Shift high half to low half
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
  %}

  // Source hi half of long
  enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
    // Encode a reg-reg copy.  If it is useless, then empty encoding.
    if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
      emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
  %}

  enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
  %}

  enc_class enc_to_bool( iRegI src, iRegI dst ) %{
    emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
  %}

  enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
    emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
    // clear if nothing else is happening
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
    // blt,a,pn done
    emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
    // mov dst,-1 in delay slot
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
  %}

  enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
  %}

  enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
  %}

  enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
  %}

  enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
    emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
  %}

  enc_class move_return_pc_to_o1() %{
    emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
  %}

#ifdef _LP64
  /* %%% merge with enc_to_bool */
  enc_class enc_convP2B( iRegI dst, iRegP src ) %{
    MacroAssembler _masm(&cbuf);

    Register   src_reg = reg_to_register_object($src$$reg);
    Register   dst_reg = reg_to_register_object($dst$$reg);
    __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
  %}
#endif

  enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
    // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
    MacroAssembler _masm(&cbuf);

    Register   p_reg = reg_to_register_object($p$$reg);
    Register   q_reg = reg_to_register_object($q$$reg);
    Register   y_reg = reg_to_register_object($y$$reg);
    Register tmp_reg = reg_to_register_object($tmp$$reg);

    __ subcc( p_reg, q_reg,   p_reg );
    __ add  ( p_reg, y_reg, tmp_reg );
    __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
  %}

  enc_class form_d2i_helper(regD src, regF dst) %{
    // fcmp %fcc0,$src,$src
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
    // branch %fcc0 not-nan, predict taken
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
    // fdtoi $src,$dst
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
    // fitos $dst,$dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
    // clear $dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
    // carry on here...
  %}

  enc_class form_d2l_helper(regD src, regD dst) %{
    // fcmp %fcc0,$src,$src  check for NAN
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
    // branch %fcc0 not-nan, predict taken
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
    // fdtox $src,$dst   convert in delay slot
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
    // fxtod $dst,$dst  (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
    // clear $dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
    // carry on here...
  %}

  enc_class form_f2i_helper(regF src, regF dst) %{
    // fcmps %fcc0,$src,$src
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
    // branch %fcc0 not-nan, predict taken
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
    // fstoi $src,$dst
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
    // fitos $dst,$dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
    // clear $dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
    // carry on here...
  %}

  enc_class form_f2l_helper(regF src, regD dst) %{
    // fcmps %fcc0,$src,$src
    emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
    // branch %fcc0 not-nan, predict taken
    emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
    // fstox $src,$dst
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
    // fxtod $dst,$dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
    // clear $dst (if nan)
    emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
    // carry on here...
  %}

  enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
  enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
  enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
  enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}

  enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}

  enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
  enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}

  enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
  %}

  enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
    emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
  %}

  enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
    emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
  %}

  enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
    emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
  %}

  enc_class form3_convI2F(regF rs2, regF rd) %{
    emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
  %}

  // Encloding class for traceable jumps
  enc_class form_jmpl(g3RegP dest) %{
    emit_jmpl(cbuf, $dest$$reg);
  %}

  enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
    emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
  %}

  enc_class form2_nop() %{
    emit_nop(cbuf);
  %}

  enc_class form2_illtrap() %{
    emit_illtrap(cbuf);
  %}


  // Compare longs and convert into -1, 0, 1.
  enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
    // CMP $src1,$src2
    emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
    // blt,a,pn done
    emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
    // mov dst,-1 in delay slot
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
    // bgt,a,pn done
    emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
    // mov dst,1 in delay slot
    emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
    // CLR    $dst
    emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
  %}

  enc_class enc_PartialSubtypeCheck() %{
    MacroAssembler _masm(&cbuf);
    __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
    __ delayed()->nop();
  %}

  enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *($labl$$label);
    Assembler::Predict predict_taken =
      cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;

    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L);
    __ delayed()->nop();
  %}

  enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *($labl$$label);
    Assembler::Predict predict_taken =
      cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;

    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L);
    __ delayed()->nop();
  %}

  enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *($labl$$label);
    Assembler::Predict predict_taken =
      cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;

    __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L);
    __ delayed()->nop();
  %}

  enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *($labl$$label);
    Assembler::Predict predict_taken =
      cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;

    __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L);
    __ delayed()->nop();
  %}

  enc_class jump_enc( iRegX switch_val, o7RegI table) %{
    MacroAssembler _masm(&cbuf);

    Register switch_reg       = as_Register($switch_val$$reg);
    Register table_reg        = O7;

    address table_base = __ address_table_constant(_index2label);
    RelocationHolder rspec = internal_word_Relocation::spec(table_base);

2270 2271
    // Move table address into a register.
    __ set(table_base, table_reg, rspec);
D
duke 已提交
2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409

    // Jump to base address + switch value
    __ ld_ptr(table_reg, switch_reg, table_reg);
    __ jmp(table_reg, G0);
    __ delayed()->nop();

  %}

  enc_class enc_ba( Label labl ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *($labl$$label);
    __ ba(false, L);
    __ delayed()->nop();
  %}

  enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{
    MacroAssembler _masm(&cbuf);
    Label &L = *$labl$$label;
    Assembler::Predict predict_taken =
      cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn;

    __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L);
    __ delayed()->nop();
  %}

  enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (1 << 18) |                    // cc2 bit for 'icc'
             ($cmp$$cmpcode << 14) |
             (0 << 13) |                    // select register move
             ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
    int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (1 << 18) |                    // cc2 bit for 'icc'
             ($cmp$$cmpcode << 14) |
             (1 << 13) |                    // select immediate move
             ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
             (simm11 << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (0 << 18) |                    // cc2 bit for 'fccX'
             ($cmp$$cmpcode << 14) |
             (0 << 13) |                    // select register move
             ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
    int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (0 << 18) |                    // cc2 bit for 'fccX'
             ($cmp$$cmpcode << 14) |
             (1 << 13) |                    // select immediate move
             ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
             (simm11 << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::fpop2_op3 << 19) |
             (0 << 18) |
             ($cmp$$cmpcode << 14) |
             (1 << 13) |                    // select register move
             ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
             ($primary << 5) |              // select single, double or quad
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::fpop2_op3 << 19) |
             (0 << 18) |
             ($cmp$$cmpcode << 14) |
             ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
             ($primary << 5) |              // select single, double or quad
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  // Used by the MIN/MAX encodings.  Same as a CMOV, but
  // the condition comes from opcode-field instead of an argument.
  enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (1 << 18) |                    // cc2 bit for 'icc'
             ($primary << 14) |
             (0 << 13) |                    // select register move
             (0 << 11) |                    // cc1, cc0 bits for 'icc'
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
    int op = (Assembler::arith_op << 30) |
             ($dst$$reg << 25) |
             (Assembler::movcc_op3 << 19) |
             (6 << 16) |                    // cc2 bit for 'xcc'
             ($primary << 14) |
             (0 << 13) |                    // select register move
             (0 << 11) |                    // cc1, cc0 bits for 'icc'
             ($src$$reg << 0);
    *((int*)(cbuf.code_end())) = op;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  // Utility encoding for loading a 64 bit Pointer into a register
  // The 64 bit pointer is stored in the generated code stream
  enc_class SetPtr( immP src, iRegP rd ) %{
    Register dest = reg_to_register_object($rd$$reg);
2410
    MacroAssembler _masm(&cbuf);
D
duke 已提交
2411 2412 2413 2414 2415
    // [RGV] This next line should be generated from ADLC
    if ( _opnds[1]->constant_is_oop() ) {
      intptr_t val = $src$$constant;
      __ set_oop_constant((jobject)val, dest);
    } else {          // non-oop pointers, e.g. card mark base, heap top
2416
      __ set($src$$constant, dest);
D
duke 已提交
2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
    }
  %}

  enc_class Set13( immI13 src, iRegI rd ) %{
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
  %}

  enc_class SetHi22( immI src, iRegI rd ) %{
    emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
  %}

  enc_class Set32( immI src, iRegI rd ) %{
    MacroAssembler _masm(&cbuf);
    __ set($src$$constant, reg_to_register_object($rd$$reg));
  %}

  enc_class SetNull( iRegI rd ) %{
    emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 );
  %}

  enc_class call_epilog %{
    if( VerifyStackAtCalls ) {
      MacroAssembler _masm(&cbuf);
      int framesize = ra_->C->frame_slots() << LogBytesPerInt;
      Register temp_reg = G3;
      __ add(SP, framesize, temp_reg);
      __ cmp(temp_reg, FP);
      __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
    }
  %}

  // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
  // to G1 so the register allocator will not have to deal with the misaligned register
  // pair.
  enc_class adjust_long_from_native_call %{
#ifndef _LP64
    if (returns_long()) {
      //    sllx  O0,32,O0
      emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
      //    srl   O1,0,O1
      emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
      //    or    O0,O1,G1
      emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
    }
#endif
  %}

  enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
    // CALL directly to the runtime
    // The user of this is responsible for ensuring that R_L7 is empty (killed).
    emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
                    /*preserve_g2=*/true, /*force far call*/true);
  %}

  enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
    // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
    // who we intended to call.
    if ( !_method ) {
      emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
    } else if (_optimized_virtual) {
      emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
    } else {
      emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
    }
    if( _method ) {  // Emit stub for static call
      emit_java_to_interp(cbuf);
    }
  %}

  enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
    MacroAssembler _masm(&cbuf);
    __ set_inst_mark();
    int vtable_index = this->_vtable_index;
    // MachCallDynamicJavaNode::ret_addr_offset uses this same test
    if (vtable_index < 0) {
      // must be invalid_vtable_index, not nonvirtual_vtable_index
      assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value");
      Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
      assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
      assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
      // !!!!!
      // Generate  "set 0x01, R_G5", placeholder instruction to load oop-info
      // emit_call_dynamic_prologue( cbuf );
      __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg);

      address  virtual_call_oop_addr = __ inst_mark();
      // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
      // who we intended to call.
      __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr));
      emit_call_reloc(cbuf, $meth$$method, relocInfo::none);
    } else {
      assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
      // Just go thru the vtable
      // get receiver klass (receiver already checked for non-null)
      // If we end up going thru a c2i adapter interpreter expects method in G5
      int off = __ offset();
2513 2514 2515
      __ load_klass(O0, G3_scratch);
      int klass_load_size;
      if (UseCompressedOops) {
2516 2517 2518 2519 2520
        assert(Universe::heap() != NULL, "java heap should be initialized");
        if (Universe::narrow_oop_base() == NULL)
          klass_load_size = 2*BytesPerInstWord;
        else
          klass_load_size = 3*BytesPerInstWord;
2521 2522 2523
      } else {
        klass_load_size = 1*BytesPerInstWord;
      }
D
duke 已提交
2524 2525 2526 2527 2528 2529 2530 2531 2532
      int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
      int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
      if( __ is_simm13(v_off) ) {
        __ ld_ptr(G3, v_off, G5_method);
      } else {
        // Generate 2 instructions
        __ Assembler::sethi(v_off & ~0x3ff, G5_method);
        __ or3(G5_method, v_off & 0x3ff, G5_method);
        // ld_ptr, set_hi, set
2533 2534
        assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
               "Unexpected instruction size(s)");
D
duke 已提交
2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706
        __ ld_ptr(G3, G5_method, G5_method);
      }
      // NOTE: for vtable dispatches, the vtable entry will never be null.
      // However it may very well end up in handle_wrong_method if the
      // method is abstract for the particular class.
      __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch);
      // jump to target (either compiled code or c2iadapter)
      __ jmpl(G3_scratch, G0, O7);
      __ delayed()->nop();
    }
  %}

  enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
    MacroAssembler _masm(&cbuf);

    Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
    Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
                              // we might be calling a C2I adapter which needs it.

    assert(temp_reg != G5_ic_reg, "conflicting registers");
    // Load nmethod
    __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg);

    // CALL to compiled java, indirect the contents of G3
    __ set_inst_mark();
    __ callr(temp_reg, G0);
    __ delayed()->nop();
  %}

enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
    MacroAssembler _masm(&cbuf);
    Register Rdividend = reg_to_register_object($src1$$reg);
    Register Rdivisor = reg_to_register_object($src2$$reg);
    Register Rresult = reg_to_register_object($dst$$reg);

    __ sra(Rdivisor, 0, Rdivisor);
    __ sra(Rdividend, 0, Rdividend);
    __ sdivx(Rdividend, Rdivisor, Rresult);
%}

enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
    MacroAssembler _masm(&cbuf);

    Register Rdividend = reg_to_register_object($src1$$reg);
    int divisor = $imm$$constant;
    Register Rresult = reg_to_register_object($dst$$reg);

    __ sra(Rdividend, 0, Rdividend);
    __ sdivx(Rdividend, divisor, Rresult);
%}

enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
    MacroAssembler _masm(&cbuf);
    Register Rsrc1 = reg_to_register_object($src1$$reg);
    Register Rsrc2 = reg_to_register_object($src2$$reg);
    Register Rdst  = reg_to_register_object($dst$$reg);

    __ sra( Rsrc1, 0, Rsrc1 );
    __ sra( Rsrc2, 0, Rsrc2 );
    __ mulx( Rsrc1, Rsrc2, Rdst );
    __ srlx( Rdst, 32, Rdst );
%}

enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
    MacroAssembler _masm(&cbuf);
    Register Rdividend = reg_to_register_object($src1$$reg);
    Register Rdivisor = reg_to_register_object($src2$$reg);
    Register Rresult = reg_to_register_object($dst$$reg);
    Register Rscratch = reg_to_register_object($scratch$$reg);

    assert(Rdividend != Rscratch, "");
    assert(Rdivisor  != Rscratch, "");

    __ sra(Rdividend, 0, Rdividend);
    __ sra(Rdivisor, 0, Rdivisor);
    __ sdivx(Rdividend, Rdivisor, Rscratch);
    __ mulx(Rscratch, Rdivisor, Rscratch);
    __ sub(Rdividend, Rscratch, Rresult);
%}

enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
    MacroAssembler _masm(&cbuf);

    Register Rdividend = reg_to_register_object($src1$$reg);
    int divisor = $imm$$constant;
    Register Rresult = reg_to_register_object($dst$$reg);
    Register Rscratch = reg_to_register_object($scratch$$reg);

    assert(Rdividend != Rscratch, "");

    __ sra(Rdividend, 0, Rdividend);
    __ sdivx(Rdividend, divisor, Rscratch);
    __ mulx(Rscratch, divisor, Rscratch);
    __ sub(Rdividend, Rscratch, Rresult);
%}

enc_class fabss (sflt_reg dst, sflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);

    __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
%}

enc_class fabsd (dflt_reg dst, dflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);

    __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
%}

enc_class fnegd (dflt_reg dst, dflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);

    __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
%}

enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);

    __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
%}

enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);

    __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
%}

enc_class fmovs (dflt_reg dst, dflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);

    __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
%}

enc_class fmovd (dflt_reg dst, dflt_reg src) %{
    MacroAssembler _masm(&cbuf);

    FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
    FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);

    __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
%}

enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
    MacroAssembler _masm(&cbuf);

    Register Roop  = reg_to_register_object($oop$$reg);
    Register Rbox  = reg_to_register_object($box$$reg);
    Register Rscratch = reg_to_register_object($scratch$$reg);
    Register Rmark =    reg_to_register_object($scratch2$$reg);

    assert(Roop  != Rscratch, "");
    assert(Roop  != Rmark, "");
    assert(Rbox  != Rscratch, "");
    assert(Rbox  != Rmark, "");

2707
    __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
D
duke 已提交
2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722
%}

enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
    MacroAssembler _masm(&cbuf);

    Register Roop  = reg_to_register_object($oop$$reg);
    Register Rbox  = reg_to_register_object($box$$reg);
    Register Rscratch = reg_to_register_object($scratch$$reg);
    Register Rmark =    reg_to_register_object($scratch2$$reg);

    assert(Roop  != Rscratch, "");
    assert(Roop  != Rmark, "");
    assert(Rbox  != Rscratch, "");
    assert(Rbox  != Rmark, "");

2723
    __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
D
duke 已提交
2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734
  %}

  enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
    MacroAssembler _masm(&cbuf);
    Register Rmem = reg_to_register_object($mem$$reg);
    Register Rold = reg_to_register_object($old$$reg);
    Register Rnew = reg_to_register_object($new$$reg);

    // casx_under_lock picks 1 of 3 encodings:
    // For 32-bit pointers you get a 32-bit CAS
    // For 64-bit pointers you get a 64-bit CASX
2735
    __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
D
duke 已提交
2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807
    __ cmp( Rold, Rnew );
  %}

  enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
    Register Rmem = reg_to_register_object($mem$$reg);
    Register Rold = reg_to_register_object($old$$reg);
    Register Rnew = reg_to_register_object($new$$reg);

    MacroAssembler _masm(&cbuf);
    __ mov(Rnew, O7);
    __ casx(Rmem, Rold, O7);
    __ cmp( Rold, O7 );
  %}

  // raw int cas, used for compareAndSwap
  enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
    Register Rmem = reg_to_register_object($mem$$reg);
    Register Rold = reg_to_register_object($old$$reg);
    Register Rnew = reg_to_register_object($new$$reg);

    MacroAssembler _masm(&cbuf);
    __ mov(Rnew, O7);
    __ cas(Rmem, Rold, O7);
    __ cmp( Rold, O7 );
  %}

  enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
    Register Rres = reg_to_register_object($res$$reg);

    MacroAssembler _masm(&cbuf);
    __ mov(1, Rres);
    __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
  %}

  enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
    Register Rres = reg_to_register_object($res$$reg);

    MacroAssembler _masm(&cbuf);
    __ mov(1, Rres);
    __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
  %}

  enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
    MacroAssembler _masm(&cbuf);
    Register Rdst = reg_to_register_object($dst$$reg);
    FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
                                     : reg_to_DoubleFloatRegister_object($src1$$reg);
    FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
                                     : reg_to_DoubleFloatRegister_object($src2$$reg);

    // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
    __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
  %}

  enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{   // Load Immediate
    MacroAssembler _masm(&cbuf);
    Register dest = reg_to_register_object($dst$$reg);
    Register temp = reg_to_register_object($tmp$$reg);
    __ set64( $src$$constant, dest, temp );
  %}

  enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{
    // Load a constant replicated "count" times with width "width"
    int bit_width = $width$$constant * 8;
    jlong elt_val = $src$$constant;
    elt_val  &= (((jlong)1) << bit_width) - 1; // mask off sign bits
    jlong val = elt_val;
    for (int i = 0; i < $count$$constant - 1; i++) {
        val <<= bit_width;
        val |= elt_val;
    }
    jdouble dval = *(jdouble*)&val; // coerce to double type
2808 2809
    MacroAssembler _masm(&cbuf);
    address double_address = __ double_constant(dval);
D
duke 已提交
2810
    RelocationHolder rspec = internal_word_Relocation::spec(double_address);
2811
    AddressLiteral addrlit(double_address, rspec);
D
duke 已提交
2812

2813
    __ sethi(addrlit, $tmp$$Register);
2814 2815 2816
    // XXX This is a quick fix for 6833573.
    //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
    __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
D
duke 已提交
2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855
  %}

  // Compiler ensures base is doubleword aligned and cnt is count of doublewords
  enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{
    MacroAssembler _masm(&cbuf);
    Register    nof_bytes_arg   = reg_to_register_object($cnt$$reg);
    Register    nof_bytes_tmp    = reg_to_register_object($temp$$reg);
    Register    base_pointer_arg = reg_to_register_object($base$$reg);

    Label loop;
    __ mov(nof_bytes_arg, nof_bytes_tmp);

    // Loop and clear, walking backwards through the array.
    // nof_bytes_tmp (if >0) is always the number of bytes to zero
    __ bind(loop);
    __ deccc(nof_bytes_tmp, 8);
    __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
    __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
    // %%%% this mini-loop must not cross a cache boundary!
  %}


  enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
    Label Ldone, Lloop;
    MacroAssembler _masm(&cbuf);

    Register   str1_reg = reg_to_register_object($str1$$reg);
    Register   str2_reg = reg_to_register_object($str2$$reg);
    Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
    Register   tmp2_reg = reg_to_register_object($tmp2$$reg);
    Register result_reg = reg_to_register_object($result$$reg);

    // Get the first character position in both strings
    //         [8] char array, [12] offset, [16] count
    int  value_offset = java_lang_String:: value_offset_in_bytes();
    int offset_offset = java_lang_String::offset_offset_in_bytes();
    int  count_offset = java_lang_String:: count_offset_in_bytes();

    // load str1 (jchar*) base address into tmp1_reg
2856 2857
    __ load_heap_oop(str1_reg, value_offset, tmp1_reg);
    __ ld(str1_reg, offset_offset, result_reg);
D
duke 已提交
2858
    __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2859
    __   ld(str1_reg, count_offset, str1_reg); // hoisted
D
duke 已提交
2860
    __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2861
    __   load_heap_oop(str2_reg, value_offset, tmp2_reg); // hoisted
D
duke 已提交
2862 2863 2864
    __ add(result_reg, tmp1_reg, tmp1_reg);

    // load str2 (jchar*) base address into tmp2_reg
2865 2866
    // __ ld_ptr(str2_reg, value_offset, tmp2_reg); // hoisted
    __ ld(str2_reg, offset_offset, result_reg);
D
duke 已提交
2867
    __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2868
    __   ld(str2_reg, count_offset, str2_reg); // hoisted
D
duke 已提交
2869 2870 2871 2872 2873 2874 2875 2876
    __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
    __   subcc(str1_reg, str2_reg, O7); // hoisted
    __ add(result_reg, tmp2_reg, tmp2_reg);

    // Compute the minimum of the string lengths(str1_reg) and the
    // difference of the string lengths (stack)

    // discard string base pointers, after loading up the lengths
2877 2878
    // __ ld(str1_reg, count_offset, str1_reg); // hoisted
    // __ ld(str2_reg, count_offset, str2_reg); // hoisted
D
duke 已提交
2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957

    // See if the lengths are different, and calculate min in str1_reg.
    // Stash diff in O7 in case we need it for a tie-breaker.
    Label Lskip;
    // __ subcc(str1_reg, str2_reg, O7); // hoisted
    __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
    __ br(Assembler::greater, true, Assembler::pt, Lskip);
    // str2 is shorter, so use its count:
    __ delayed()->sll(str2_reg, exact_log2(sizeof(jchar)), str1_reg); // scale the limit
    __ bind(Lskip);

    // reallocate str1_reg, str2_reg, result_reg
    // Note:  limit_reg holds the string length pre-scaled by 2
    Register limit_reg =   str1_reg;
    Register  chr2_reg =   str2_reg;
    Register  chr1_reg = result_reg;
    // tmp{12} are the base pointers

    // Is the minimum length zero?
    __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
    __ delayed()->mov(O7, result_reg);  // result is difference in lengths

    // Load first characters
    __ lduh(tmp1_reg, 0, chr1_reg);
    __ lduh(tmp2_reg, 0, chr2_reg);

    // Compare first characters
    __ subcc(chr1_reg, chr2_reg, chr1_reg);
    __ br(Assembler::notZero, false, Assembler::pt,  Ldone);
    assert(chr1_reg == result_reg, "result must be pre-placed");
    __ delayed()->nop();

    {
      // Check after comparing first character to see if strings are equivalent
      Label LSkip2;
      // Check if the strings start at same location
      __ cmp(tmp1_reg, tmp2_reg);
      __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
      __ delayed()->nop();

      // Check if the length difference is zero (in O7)
      __ cmp(G0, O7);
      __ br(Assembler::equal, true, Assembler::pn, Ldone);
      __ delayed()->mov(G0, result_reg);  // result is zero

      // Strings might not be equal
      __ bind(LSkip2);
    }

    __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
    __ delayed()->mov(O7, result_reg);  // result is difference in lengths

    // Shift tmp1_reg and tmp2_reg to the end of the arrays, negate limit
    __ add(tmp1_reg, limit_reg, tmp1_reg);
    __ add(tmp2_reg, limit_reg, tmp2_reg);
    __ neg(chr1_reg, limit_reg);  // limit = -(limit-2)

    // Compare the rest of the characters
    __ lduh(tmp1_reg, limit_reg, chr1_reg);
    __ bind(Lloop);
    // __ lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted
    __ lduh(tmp2_reg, limit_reg, chr2_reg);
    __ subcc(chr1_reg, chr2_reg, chr1_reg);
    __ br(Assembler::notZero, false, Assembler::pt, Ldone);
    assert(chr1_reg == result_reg, "result must be pre-placed");
    __ delayed()->inccc(limit_reg, sizeof(jchar));
    // annul LDUH if branch is not taken to prevent access past end of string
    __ br(Assembler::notZero, true, Assembler::pt, Lloop);
    __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted

    // If strings are equal up to min length, return the length difference.
    __ mov(O7, result_reg);

    // Otherwise, return the difference between the first mismatched chars.
    __ bind(Ldone);
  %}

C
cfang 已提交
2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974
enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
    Label Lword, Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone;
    MacroAssembler _masm(&cbuf);

    Register   str1_reg = reg_to_register_object($str1$$reg);
    Register   str2_reg = reg_to_register_object($str2$$reg);
    Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
    Register   tmp2_reg = reg_to_register_object($tmp2$$reg);
    Register result_reg = reg_to_register_object($result$$reg);

    // Get the first character position in both strings
    //         [8] char array, [12] offset, [16] count
    int  value_offset = java_lang_String:: value_offset_in_bytes();
    int offset_offset = java_lang_String::offset_offset_in_bytes();
    int  count_offset = java_lang_String:: count_offset_in_bytes();

    // load str1 (jchar*) base address into tmp1_reg
2975 2976
    __ load_heap_oop(Address(str1_reg, value_offset), tmp1_reg);
    __ ld(Address(str1_reg, offset_offset), result_reg);
C
cfang 已提交
2977
    __ add(tmp1_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1_reg);
2978
    __    ld(Address(str1_reg, count_offset), str1_reg); // hoisted
C
cfang 已提交
2979
    __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
2980
    __    load_heap_oop(Address(str2_reg, value_offset), tmp2_reg); // hoisted
C
cfang 已提交
2981 2982 2983
    __ add(result_reg, tmp1_reg, tmp1_reg);

    // load str2 (jchar*) base address into tmp2_reg
2984 2985
    // __ ld_ptr(Address(str2_reg, value_offset), tmp2_reg); // hoisted
    __ ld(Address(str2_reg, offset_offset), result_reg);
C
cfang 已提交
2986
    __ add(tmp2_reg, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp2_reg);
2987
    __    ld(Address(str2_reg, count_offset), str2_reg); // hoisted
C
cfang 已提交
2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093
    __ sll(result_reg, exact_log2(sizeof(jchar)), result_reg);
    __   cmp(str1_reg, str2_reg); // hoisted
    __ add(result_reg, tmp2_reg, tmp2_reg);

    __ sll(str1_reg, exact_log2(sizeof(jchar)), str1_reg);
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg);    // not equal

    __ br_zero(Assembler::equal, true, Assembler::pn, str1_reg, Ldone);
    __ delayed()->add(G0, 1, result_reg); //equals

    __ cmp(tmp1_reg, tmp2_reg); //same string ?
    __ brx(Assembler::equal, true, Assembler::pn, Ldone);
    __ delayed()->add(G0, 1, result_reg);

    //rename registers
    Register limit_reg =   str1_reg;
    Register  chr2_reg =   str2_reg;
    Register  chr1_reg = result_reg;
    // tmp{12} are the base pointers

    //check for alignment and position the pointers to the ends
    __ or3(tmp1_reg, tmp2_reg, chr1_reg);
    __ andcc(chr1_reg, 0x3, chr1_reg); // notZero means at least one not 4-byte aligned
    __ br(Assembler::notZero, false, Assembler::pn, Lchar);
    __ delayed()->nop();

    __ bind(Lword);
    __ and3(limit_reg, 0x2, O7); //remember the remainder (either 0 or 2)
    __ andn(limit_reg, 0x3, limit_reg);
    __ br_zero(Assembler::zero, false, Assembler::pn, limit_reg, Lpost_word);
    __ delayed()->nop();

    __ add(tmp1_reg, limit_reg, tmp1_reg);
    __ add(tmp2_reg, limit_reg, tmp2_reg);
    __ neg(limit_reg);

    __ lduw(tmp1_reg, limit_reg, chr1_reg);
    __ bind(Lword_loop);
    __ lduw(tmp2_reg, limit_reg, chr2_reg);
    __ cmp(chr1_reg, chr2_reg);
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg);
    __ inccc(limit_reg, 2*sizeof(jchar));
    // annul LDUW if branch i  s not taken to prevent access past end of string
    __ br(Assembler::notZero, true, Assembler::pt, Lword_loop); //annul on taken
    __ delayed()->lduw(tmp1_reg, limit_reg, chr1_reg); // hoisted

    __ bind(Lpost_word);
    __ br_zero(Assembler::zero, true, Assembler::pt, O7, Ldone);
    __ delayed()->add(G0, 1, result_reg);

    __ lduh(tmp1_reg, 0, chr1_reg);
    __ lduh(tmp2_reg, 0, chr2_reg);
    __ cmp (chr1_reg, chr2_reg);
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg);
    __ ba(false,Ldone);
    __ delayed()->add(G0, 1, result_reg);

    __ bind(Lchar);
    __ add(tmp1_reg, limit_reg, tmp1_reg);
    __ add(tmp2_reg, limit_reg, tmp2_reg);
    __ neg(limit_reg); //negate count

    __ lduh(tmp1_reg, limit_reg, chr1_reg);
    __ bind(Lchar_loop);
    __ lduh(tmp2_reg, limit_reg, chr2_reg);
    __ cmp(chr1_reg, chr2_reg);
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg); //not equal
    __ inccc(limit_reg, sizeof(jchar));
    // annul LDUH if branch is not taken to prevent access past end of string
    __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); //annul on taken
    __ delayed()->lduh(tmp1_reg, limit_reg, chr1_reg); // hoisted

    __ add(G0, 1, result_reg);  //equal

    __ bind(Ldone);
  %}

enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result) %{
    Label Lvector, Ldone, Lloop;
    MacroAssembler _masm(&cbuf);

    Register   ary1_reg = reg_to_register_object($ary1$$reg);
    Register   ary2_reg = reg_to_register_object($ary2$$reg);
    Register   tmp1_reg = reg_to_register_object($tmp1$$reg);
    Register   tmp2_reg = reg_to_register_object($tmp2$$reg);
    Register result_reg = reg_to_register_object($result$$reg);

    int length_offset  = arrayOopDesc::length_offset_in_bytes();
    int base_offset    = arrayOopDesc::base_offset_in_bytes(T_CHAR);

    // return true if the same array
    __ cmp(ary1_reg, ary2_reg);
    __ br(Assembler::equal, true, Assembler::pn, Ldone);
    __ delayed()->add(G0, 1, result_reg); // equal

    __ br_null(ary1_reg, true, Assembler::pn, Ldone);
    __ delayed()->mov(G0, result_reg);    // not equal

    __ br_null(ary2_reg, true, Assembler::pn, Ldone);
    __ delayed()->mov(G0, result_reg);    // not equal

    //load the lengths of arrays
3094 3095
    __ ld(Address(ary1_reg, length_offset), tmp1_reg);
    __ ld(Address(ary2_reg, length_offset), tmp2_reg);
C
cfang 已提交
3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153

    // return false if the two arrays are not equal length
    __ cmp(tmp1_reg, tmp2_reg);
    __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
    __ delayed()->mov(G0, result_reg);     // not equal

    __ br_zero(Assembler::zero, true, Assembler::pn, tmp1_reg, Ldone);
    __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal

    // load array addresses
    __ add(ary1_reg, base_offset, ary1_reg);
    __ add(ary2_reg, base_offset, ary2_reg);

    // renaming registers
    Register chr1_reg  =  tmp2_reg;   // for characters in ary1
    Register chr2_reg  =  result_reg; // for characters in ary2
    Register limit_reg =  tmp1_reg;   // length

    // set byte count
    __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
    __ andcc(limit_reg, 0x2, chr1_reg); //trailing character ?
    __ br(Assembler::zero, false, Assembler::pt, Lvector);
    __ delayed()->nop();

    //compare the trailing char
    __ sub(limit_reg, sizeof(jchar), limit_reg);
    __ lduh(ary1_reg, limit_reg, chr1_reg);
    __ lduh(ary2_reg, limit_reg, chr2_reg);
    __ cmp(chr1_reg, chr2_reg);
    __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg);     // not equal

    // only one char ?
    __ br_zero(Assembler::zero, true, Assembler::pn, limit_reg, Ldone);
    __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal

    __ bind(Lvector);
    // Shift ary1_reg and ary2_reg to the end of the arrays, negate limit
    __ add(ary1_reg, limit_reg, ary1_reg);
    __ add(ary2_reg, limit_reg, ary2_reg);
    __ neg(limit_reg, limit_reg);

    __ lduw(ary1_reg, limit_reg, chr1_reg);
    __ bind(Lloop);
    __ lduw(ary2_reg, limit_reg, chr2_reg);
    __ cmp(chr1_reg, chr2_reg);
    __ br(Assembler::notEqual, false, Assembler::pt, Ldone);
    __ delayed()->mov(G0, result_reg);     // not equal
    __ inccc(limit_reg, 2*sizeof(jchar));
    // annul LDUW if branch is not taken to prevent access past end of string
    __ br(Assembler::notZero, true, Assembler::pt, Lloop); //annul on taken
    __ delayed()->lduw(ary1_reg, limit_reg, chr1_reg); // hoisted

    __ add(G0, 1, result_reg); // equals

    __ bind(Ldone);
  %}

D
duke 已提交
3154 3155 3156
  enc_class enc_rethrow() %{
    cbuf.set_inst_mark();
    Register temp_reg = G3;
3157
    AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
D
duke 已提交
3158 3159 3160 3161
    assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
    MacroAssembler _masm(&cbuf);
#ifdef ASSERT
    __ save_frame(0);
3162 3163 3164
    AddressLiteral last_rethrow_addrlit(&last_rethrow);
    __ sethi(last_rethrow_addrlit, L1);
    Address addr(L1, last_rethrow_addrlit.low10());
D
duke 已提交
3165 3166
    __ get_pc(L2);
    __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
3167
    __ st_ptr(L2, addr);
D
duke 已提交
3168 3169
    __ restore();
#endif
3170
    __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
D
duke 已提交
3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208
    __ delayed()->nop();
  %}

  enc_class emit_mem_nop() %{
    // Generates the instruction LDUXA [o6,g0],#0x82,g0
    unsigned int *code = (unsigned int*)cbuf.code_end();
    *code = (unsigned int)0xc0839040;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class emit_fadd_nop() %{
    // Generates the instruction FMOVS f31,f31
    unsigned int *code = (unsigned int*)cbuf.code_end();
    *code = (unsigned int)0xbfa0003f;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class emit_br_nop() %{
    // Generates the instruction BPN,PN .
    unsigned int *code = (unsigned int*)cbuf.code_end();
    *code = (unsigned int)0x00400000;
    cbuf.set_code_end(cbuf.code_end() + BytesPerInstWord);
  %}

  enc_class enc_membar_acquire %{
    MacroAssembler _masm(&cbuf);
    __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
  %}

  enc_class enc_membar_release %{
    MacroAssembler _masm(&cbuf);
    __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
  %}

  enc_class enc_membar_volatile %{
    MacroAssembler _masm(&cbuf);
    __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
  %}
3209

D
duke 已提交
3210 3211 3212 3213 3214 3215 3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382
  enc_class enc_repl8b( iRegI src, iRegL dst ) %{
    MacroAssembler _masm(&cbuf);
    Register src_reg = reg_to_register_object($src$$reg);
    Register dst_reg = reg_to_register_object($dst$$reg);
    __ sllx(src_reg, 56, dst_reg);
    __ srlx(dst_reg,  8, O7);
    __ or3 (dst_reg, O7, dst_reg);
    __ srlx(dst_reg, 16, O7);
    __ or3 (dst_reg, O7, dst_reg);
    __ srlx(dst_reg, 32, O7);
    __ or3 (dst_reg, O7, dst_reg);
  %}

  enc_class enc_repl4b( iRegI src, iRegL dst ) %{
    MacroAssembler _masm(&cbuf);
    Register src_reg = reg_to_register_object($src$$reg);
    Register dst_reg = reg_to_register_object($dst$$reg);
    __ sll(src_reg, 24, dst_reg);
    __ srl(dst_reg,  8, O7);
    __ or3(dst_reg, O7, dst_reg);
    __ srl(dst_reg, 16, O7);
    __ or3(dst_reg, O7, dst_reg);
  %}

  enc_class enc_repl4s( iRegI src, iRegL dst ) %{
    MacroAssembler _masm(&cbuf);
    Register src_reg = reg_to_register_object($src$$reg);
    Register dst_reg = reg_to_register_object($dst$$reg);
    __ sllx(src_reg, 48, dst_reg);
    __ srlx(dst_reg, 16, O7);
    __ or3 (dst_reg, O7, dst_reg);
    __ srlx(dst_reg, 32, O7);
    __ or3 (dst_reg, O7, dst_reg);
  %}

  enc_class enc_repl2i( iRegI src, iRegL dst ) %{
    MacroAssembler _masm(&cbuf);
    Register src_reg = reg_to_register_object($src$$reg);
    Register dst_reg = reg_to_register_object($dst$$reg);
    __ sllx(src_reg, 32, dst_reg);
    __ srlx(dst_reg, 32, O7);
    __ or3 (dst_reg, O7, dst_reg);
  %}

%}

//----------FRAME--------------------------------------------------------------
// Definition of frame structure and management information.
//
//  S T A C K   L A Y O U T    Allocators stack-slot number
//                             |   (to get allocators register number
//  G  Owned by    |        |  v    add VMRegImpl::stack0)
//  r   CALLER     |        |
//  o     |        +--------+      pad to even-align allocators stack-slot
//  w     V        |  pad0  |        numbers; owned by CALLER
//  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
//  h     ^        |   in   |  5
//        |        |  args  |  4   Holes in incoming args owned by SELF
//  |     |        |        |  3
//  |     |        +--------+
//  V     |        | old out|      Empty on Intel, window on Sparc
//        |    old |preserve|      Must be even aligned.
//        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
//        |        |   in   |  3   area for Intel ret address
//     Owned by    |preserve|      Empty on Sparc.
//       SELF      +--------+
//        |        |  pad2  |  2   pad to align old SP
//        |        +--------+  1
//        |        | locks  |  0
//        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
//        |        |  pad1  | 11   pad to align new SP
//        |        +--------+
//        |        |        | 10
//        |        | spills |  9   spills
//        V        |        |  8   (pad0 slot for callee)
//      -----------+--------+----> Matcher::_out_arg_limit, unaligned
//        ^        |  out   |  7
//        |        |  args  |  6   Holes in outgoing args owned by CALLEE
//     Owned by    +--------+
//      CALLEE     | new out|  6   Empty on Intel, window on Sparc
//        |    new |preserve|      Must be even-aligned.
//        |     SP-+--------+----> Matcher::_new_SP, even aligned
//        |        |        |
//
// Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
//         known from SELF's arguments and the Java calling convention.
//         Region 6-7 is determined per call site.
// Note 2: If the calling convention leaves holes in the incoming argument
//         area, those holes are owned by SELF.  Holes in the outgoing area
//         are owned by the CALLEE.  Holes should not be nessecary in the
//         incoming area, as the Java calling convention is completely under
//         the control of the AD file.  Doubles can be sorted and packed to
//         avoid holes.  Holes in the outgoing arguments may be nessecary for
//         varargs C calling conventions.
// Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
//         even aligned with pad0 as needed.
//         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
//         region 6-11 is even aligned; it may be padded out more so that
//         the region from SP to FP meets the minimum stack alignment.

frame %{
  // What direction does stack grow in (assumed to be same for native & Java)
  stack_direction(TOWARDS_LOW);

  // These two registers define part of the calling convention
  // between compiled code and the interpreter.
  inline_cache_reg(R_G5);                // Inline Cache Register or methodOop for I2C
  interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter

  // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
  cisc_spilling_operand_name(indOffset);

  // Number of stack slots consumed by a Monitor enter
#ifdef _LP64
  sync_stack_slots(2);
#else
  sync_stack_slots(1);
#endif

  // Compiled code's Frame Pointer
  frame_pointer(R_SP);

  // Stack alignment requirement
  stack_alignment(StackAlignmentInBytes);
  //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
  // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)

  // Number of stack slots between incoming argument block and the start of
  // a new frame.  The PROLOG must add this many slots to the stack.  The
  // EPILOG must remove this many slots.
  in_preserve_stack_slots(0);

  // Number of outgoing stack slots killed above the out_preserve_stack_slots
  // for calls to C.  Supports the var-args backing area for register parms.
  // ADLC doesn't support parsing expressions, so I folded the math by hand.
#ifdef _LP64
  // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
  varargs_C_out_slots_killed(12);
#else
  // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
  varargs_C_out_slots_killed( 7);
#endif

  // The after-PROLOG location of the return address.  Location of
  // return address specifies a type (REG or STACK) and a number
  // representing the register number (i.e. - use a register name) or
  // stack slot.
  return_addr(REG R_I7);          // Ret Addr is in register I7

  // Body of function which returns an OptoRegs array locating
  // arguments either in registers or in stack slots for calling
  // java
  calling_convention %{
    (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);

  %}

  // Body of function which returns an OptoRegs array locating
  // arguments either in registers or in stack slots for callin
  // C.
  c_calling_convention %{
    // This is obviously always outgoing
    (void) SharedRuntime::c_calling_convention(sig_bt, regs, length);
  %}

  // Location of native (C/C++) and interpreter return values.  This is specified to
  // be the  same as Java.  In the 32-bit VM, long values are actually returned from
  // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
  // to and from the register pairs is done by the appropriate call and epilog
  // opcodes.  This simplifies the register allocator.
  c_return_value %{
    assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
#ifdef     _LP64
3383 3384 3385 3386
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
D
duke 已提交
3387
#else  // !_LP64
3388 3389 3390 3391
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
D
duke 已提交
3392 3393 3394 3395 3396 3397 3398 3399 3400
#endif
    return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
                        (is_outgoing?lo_out:lo_in)[ideal_reg] );
  %}

  // Location of compiled Java return values.  Same as C
  return_value %{
    assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
#ifdef     _LP64
3401 3402 3403 3404
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
D
duke 已提交
3405
#else  // !_LP64
3406 3407 3408 3409
    static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
    static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
    static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
    static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
D
duke 已提交
3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601
#endif
    return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
                        (is_outgoing?lo_out:lo_in)[ideal_reg] );
  %}

%}


//----------ATTRIBUTES---------------------------------------------------------
//----------Operand Attributes-------------------------------------------------
op_attrib op_cost(1);          // Required cost attribute

//----------Instruction Attributes---------------------------------------------
ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
ins_attrib ins_size(32);       // Required size attribute (in bits)
ins_attrib ins_pc_relative(0); // Required PC Relative flag
ins_attrib ins_short_branch(0); // Required flag: is this instruction a
                                // non-matching short branch variant of some
                                                            // long branch?

//----------OPERANDS-----------------------------------------------------------
// Operand definitions must precede instruction definitions for correct parsing
// in the ADLC because operands constitute user defined types which are used in
// instruction definitions.

//----------Simple Operands----------------------------------------------------
// Immediate Operands
// Integer Immediate: 32-bit
operand immI() %{
  match(ConI);

  op_cost(0);
  // formats are generated automatically for constants and base registers
  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: 13-bit
operand immI13() %{
  predicate(Assembler::is_simm13(n->get_int()));
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Unsigned (positive) Integer Immediate: 13-bit
operand immU13() %{
  predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: 6-bit
operand immU6() %{
  predicate(n->get_int() >= 0 && n->get_int() <= 63);
  match(ConI);
  op_cost(0);
  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: 11-bit
operand immI11() %{
  predicate(Assembler::is_simm(n->get_int(),11));
  match(ConI);
  op_cost(0);
  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: 0-bit
operand immI0() %{
  predicate(n->get_int() == 0);
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: the value 10
operand immI10() %{
  predicate(n->get_int() == 10);
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: the values 0-31
operand immU5() %{
  predicate(n->get_int() >= 0 && n->get_int() <= 31);
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: the values 1-31
operand immI_1_31() %{
  predicate(n->get_int() >= 1 && n->get_int() <= 31);
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: the values 32-63
operand immI_32_63() %{
  predicate(n->get_int() >= 32 && n->get_int() <= 63);
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Integer Immediate: the value 255
operand immI_255() %{
  predicate( n->get_int() == 255 );
  match(ConI);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Long Immediate: the value FF
operand immL_FF() %{
  predicate( n->get_long() == 0xFFL );
  match(ConL);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Long Immediate: the value FFFF
operand immL_FFFF() %{
  predicate( n->get_long() == 0xFFFFL );
  match(ConL);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Pointer Immediate: 32 or 64-bit
operand immP() %{
  match(ConP);

  op_cost(5);
  // formats are generated automatically for constants and base registers
  format %{ %}
  interface(CONST_INTER);
%}

operand immP13() %{
  predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
  match(ConP);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

operand immP0() %{
  predicate(n->get_ptr() == 0);
  match(ConP);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

operand immP_poll() %{
  predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
  match(ConP);

  // formats are generated automatically for constants and base registers
  format %{ %}
  interface(CONST_INTER);
%}

3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
// Pointer Immediate
operand immN()
%{
  match(ConN);

  op_cost(10);
  format %{ %}
  interface(CONST_INTER);
%}

// NULL Pointer Immediate
operand immN0()
%{
  predicate(n->get_narrowcon() == 0);
  match(ConN);

  op_cost(0);
  format %{ %}
  interface(CONST_INTER);
%}

D
duke 已提交
3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886
operand immL() %{
  match(ConL);
  op_cost(40);
  // formats are generated automatically for constants and base registers
  format %{ %}
  interface(CONST_INTER);
%}

operand immL0() %{
  predicate(n->get_long() == 0L);
  match(ConL);
  op_cost(0);
  // formats are generated automatically for constants and base registers
  format %{ %}
  interface(CONST_INTER);
%}

// Long Immediate: 13-bit
operand immL13() %{
  predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
  match(ConL);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Long Immediate: low 32-bit mask
operand immL_32bits() %{
  predicate(n->get_long() == 0xFFFFFFFFL);
  match(ConL);
  op_cost(0);

  format %{ %}
  interface(CONST_INTER);
%}

// Double Immediate
operand immD() %{
  match(ConD);

  op_cost(40);
  format %{ %}
  interface(CONST_INTER);
%}

operand immD0() %{
#ifdef _LP64
  // on 64-bit architectures this comparision is faster
  predicate(jlong_cast(n->getd()) == 0);
#else
  predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
#endif
  match(ConD);

  op_cost(0);
  format %{ %}
  interface(CONST_INTER);
%}

// Float Immediate
operand immF() %{
  match(ConF);

  op_cost(20);
  format %{ %}
  interface(CONST_INTER);
%}

// Float Immediate: 0
operand immF0() %{
  predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
  match(ConF);

  op_cost(0);
  format %{ %}
  interface(CONST_INTER);
%}

// Integer Register Operands
// Integer Register
operand iRegI() %{
  constraint(ALLOC_IN_RC(int_reg));
  match(RegI);

  match(notemp_iRegI);
  match(g1RegI);
  match(o0RegI);
  match(iRegIsafe);

  format %{ %}
  interface(REG_INTER);
%}

operand notemp_iRegI() %{
  constraint(ALLOC_IN_RC(notemp_int_reg));
  match(RegI);

  match(o0RegI);

  format %{ %}
  interface(REG_INTER);
%}

operand o0RegI() %{
  constraint(ALLOC_IN_RC(o0_regI));
  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

// Pointer Register
operand iRegP() %{
  constraint(ALLOC_IN_RC(ptr_reg));
  match(RegP);

  match(lock_ptr_RegP);
  match(g1RegP);
  match(g2RegP);
  match(g3RegP);
  match(g4RegP);
  match(i0RegP);
  match(o0RegP);
  match(o1RegP);
  match(l7RegP);

  format %{ %}
  interface(REG_INTER);
%}

operand sp_ptr_RegP() %{
  constraint(ALLOC_IN_RC(sp_ptr_reg));
  match(RegP);
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand lock_ptr_RegP() %{
  constraint(ALLOC_IN_RC(lock_ptr_reg));
  match(RegP);
  match(i0RegP);
  match(o0RegP);
  match(o1RegP);
  match(l7RegP);

  format %{ %}
  interface(REG_INTER);
%}

operand g1RegP() %{
  constraint(ALLOC_IN_RC(g1_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand g2RegP() %{
  constraint(ALLOC_IN_RC(g2_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand g3RegP() %{
  constraint(ALLOC_IN_RC(g3_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand g1RegI() %{
  constraint(ALLOC_IN_RC(g1_regI));
  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

operand g3RegI() %{
  constraint(ALLOC_IN_RC(g3_regI));
  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

operand g4RegI() %{
  constraint(ALLOC_IN_RC(g4_regI));
  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

operand g4RegP() %{
  constraint(ALLOC_IN_RC(g4_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand i0RegP() %{
  constraint(ALLOC_IN_RC(i0_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand o0RegP() %{
  constraint(ALLOC_IN_RC(o0_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand o1RegP() %{
  constraint(ALLOC_IN_RC(o1_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand o2RegP() %{
  constraint(ALLOC_IN_RC(o2_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand o7RegP() %{
  constraint(ALLOC_IN_RC(o7_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand l7RegP() %{
  constraint(ALLOC_IN_RC(l7_regP));
  match(iRegP);

  format %{ %}
  interface(REG_INTER);
%}

operand o7RegI() %{
  constraint(ALLOC_IN_RC(o7_regI));
  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

3887 3888 3889 3890 3891 3892 3893 3894
operand iRegN() %{
  constraint(ALLOC_IN_RC(int_reg));
  match(RegN);

  format %{ %}
  interface(REG_INTER);
%}

D
duke 已提交
3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927
// Long Register
operand iRegL() %{
  constraint(ALLOC_IN_RC(long_reg));
  match(RegL);

  format %{ %}
  interface(REG_INTER);
%}

operand o2RegL() %{
  constraint(ALLOC_IN_RC(o2_regL));
  match(iRegL);

  format %{ %}
  interface(REG_INTER);
%}

operand o7RegL() %{
  constraint(ALLOC_IN_RC(o7_regL));
  match(iRegL);

  format %{ %}
  interface(REG_INTER);
%}

operand g1RegL() %{
  constraint(ALLOC_IN_RC(g1_regL));
  match(iRegL);

  format %{ %}
  interface(REG_INTER);
%}

3928 3929 3930 3931 3932 3933 3934 3935
operand g3RegL() %{
  constraint(ALLOC_IN_RC(g3_regL));
  match(iRegL);

  format %{ %}
  interface(REG_INTER);
%}

D
duke 已提交
3936 3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030
// Int Register safe
// This is 64bit safe
operand iRegIsafe() %{
  constraint(ALLOC_IN_RC(long_reg));

  match(iRegI);

  format %{ %}
  interface(REG_INTER);
%}

// Condition Code Flag Register
operand flagsReg() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);

  format %{ "ccr" %} // both ICC and XCC
  interface(REG_INTER);
%}

// Condition Code Register, unsigned comparisons.
operand flagsRegU() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);

  format %{ "icc_U" %}
  interface(REG_INTER);
%}

// Condition Code Register, pointer comparisons.
operand flagsRegP() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);

#ifdef _LP64
  format %{ "xcc_P" %}
#else
  format %{ "icc_P" %}
#endif
  interface(REG_INTER);
%}

// Condition Code Register, long comparisons.
operand flagsRegL() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);

  format %{ "xcc_L" %}
  interface(REG_INTER);
%}

// Condition Code Register, floating comparisons, unordered same as "less".
operand flagsRegF() %{
  constraint(ALLOC_IN_RC(float_flags));
  match(RegFlags);
  match(flagsRegF0);

  format %{ %}
  interface(REG_INTER);
%}

operand flagsRegF0() %{
  constraint(ALLOC_IN_RC(float_flag0));
  match(RegFlags);

  format %{ %}
  interface(REG_INTER);
%}


// Condition Code Flag Register used by long compare
operand flagsReg_long_LTGE() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);
  format %{ "icc_LTGE" %}
  interface(REG_INTER);
%}
operand flagsReg_long_EQNE() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);
  format %{ "icc_EQNE" %}
  interface(REG_INTER);
%}
operand flagsReg_long_LEGT() %{
  constraint(ALLOC_IN_RC(int_flags));
  match(RegFlags);
  format %{ "icc_LEGT" %}
  interface(REG_INTER);
%}


operand regD() %{
  constraint(ALLOC_IN_RC(dflt_reg));
  match(RegD);

4031 4032
  match(regD_low);

D
duke 已提交
4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046
  format %{ %}
  interface(REG_INTER);
%}

operand regF() %{
  constraint(ALLOC_IN_RC(sflt_reg));
  match(RegF);

  format %{ %}
  interface(REG_INTER);
%}

operand regD_low() %{
  constraint(ALLOC_IN_RC(dflt_low_reg));
4047
  match(regD);
D
duke 已提交
4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310

  format %{ %}
  interface(REG_INTER);
%}

// Special Registers

// Method Register
operand inline_cache_regP(iRegP reg) %{
  constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
  match(reg);
  format %{ %}
  interface(REG_INTER);
%}

operand interpreter_method_oop_regP(iRegP reg) %{
  constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
  match(reg);
  format %{ %}
  interface(REG_INTER);
%}


//----------Complex Operands---------------------------------------------------
// Indirect Memory Reference
operand indirect(sp_ptr_RegP reg) %{
  constraint(ALLOC_IN_RC(sp_ptr_reg));
  match(reg);

  op_cost(100);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base($reg);
    index(0x0);
    scale(0x0);
    disp(0x0);
  %}
%}

// Indirect with Offset
operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
  constraint(ALLOC_IN_RC(sp_ptr_reg));
  match(AddP reg offset);

  op_cost(100);
  format %{ "[$reg + $offset]" %}
  interface(MEMORY_INTER) %{
    base($reg);
    index(0x0);
    scale(0x0);
    disp($offset);
  %}
%}

// Note:  Intel has a swapped version also, like this:
//operand indOffsetX(iRegI reg, immP offset) %{
//  constraint(ALLOC_IN_RC(int_reg));
//  match(AddP offset reg);
//
//  op_cost(100);
//  format %{ "[$reg + $offset]" %}
//  interface(MEMORY_INTER) %{
//    base($reg);
//    index(0x0);
//    scale(0x0);
//    disp($offset);
//  %}
//%}
//// However, it doesn't make sense for SPARC, since
// we have no particularly good way to embed oops in
// single instructions.

// Indirect with Register Index
operand indIndex(iRegP addr, iRegX index) %{
  constraint(ALLOC_IN_RC(ptr_reg));
  match(AddP addr index);

  op_cost(100);
  format %{ "[$addr + $index]" %}
  interface(MEMORY_INTER) %{
    base($addr);
    index($index);
    scale(0x0);
    disp(0x0);
  %}
%}

//----------Special Memory Operands--------------------------------------------
// Stack Slot Operand - This operand is used for loading and storing temporary
//                      values on the stack where a match requires a value to
//                      flow through memory.
operand stackSlotI(sRegI reg) %{
  constraint(ALLOC_IN_RC(stack_slots));
  op_cost(100);
  //match(RegI);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base(0xE);   // R_SP
    index(0x0);
    scale(0x0);
    disp($reg);  // Stack Offset
  %}
%}

operand stackSlotP(sRegP reg) %{
  constraint(ALLOC_IN_RC(stack_slots));
  op_cost(100);
  //match(RegP);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base(0xE);   // R_SP
    index(0x0);
    scale(0x0);
    disp($reg);  // Stack Offset
  %}
%}

operand stackSlotF(sRegF reg) %{
  constraint(ALLOC_IN_RC(stack_slots));
  op_cost(100);
  //match(RegF);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base(0xE);   // R_SP
    index(0x0);
    scale(0x0);
    disp($reg);  // Stack Offset
  %}
%}
operand stackSlotD(sRegD reg) %{
  constraint(ALLOC_IN_RC(stack_slots));
  op_cost(100);
  //match(RegD);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base(0xE);   // R_SP
    index(0x0);
    scale(0x0);
    disp($reg);  // Stack Offset
  %}
%}
operand stackSlotL(sRegL reg) %{
  constraint(ALLOC_IN_RC(stack_slots));
  op_cost(100);
  //match(RegL);
  format %{ "[$reg]" %}
  interface(MEMORY_INTER) %{
    base(0xE);   // R_SP
    index(0x0);
    scale(0x0);
    disp($reg);  // Stack Offset
  %}
%}

// Operands for expressing Control Flow
// NOTE:  Label is a predefined operand which should not be redefined in
//        the AD file.  It is generically handled within the ADLC.

//----------Conditional Branch Operands----------------------------------------
// Comparison Op  - This is the operation of the comparison, and is limited to
//                  the following set of codes:
//                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
//
// Other attributes of the comparison, such as unsignedness, are specified
// by the comparison instruction that sets a condition code flags register.
// That result is represented by a flags operand whose subtype is appropriate
// to the unsignedness (etc.) of the comparison.
//
// Later, the instruction which matches both the Comparison Op (a Bool) and
// the flags (produced by the Cmp) specifies the coding of the comparison op
// by matching a specific subtype of Bool operand below, such as cmpOpU.

operand cmpOp() %{
  match(Bool);

  format %{ "" %}
  interface(COND_INTER) %{
    equal(0x1);
    not_equal(0x9);
    less(0x3);
    greater_equal(0xB);
    less_equal(0x2);
    greater(0xA);
  %}
%}

// Comparison Op, unsigned
operand cmpOpU() %{
  match(Bool);

  format %{ "u" %}
  interface(COND_INTER) %{
    equal(0x1);
    not_equal(0x9);
    less(0x5);
    greater_equal(0xD);
    less_equal(0x4);
    greater(0xC);
  %}
%}

// Comparison Op, pointer (same as unsigned)
operand cmpOpP() %{
  match(Bool);

  format %{ "p" %}
  interface(COND_INTER) %{
    equal(0x1);
    not_equal(0x9);
    less(0x5);
    greater_equal(0xD);
    less_equal(0x4);
    greater(0xC);
  %}
%}

// Comparison Op, branch-register encoding
operand cmpOp_reg() %{
  match(Bool);

  format %{ "" %}
  interface(COND_INTER) %{
    equal        (0x1);
    not_equal    (0x5);
    less         (0x3);
    greater_equal(0x7);
    less_equal   (0x2);
    greater      (0x6);
  %}
%}

// Comparison Code, floating, unordered same as less
operand cmpOpF() %{
  match(Bool);

  format %{ "fl" %}
  interface(COND_INTER) %{
    equal(0x9);
    not_equal(0x1);
    less(0x3);
    greater_equal(0xB);
    less_equal(0xE);
    greater(0x6);
  %}
%}

// Used by long compare
operand cmpOp_commute() %{
  match(Bool);

  format %{ "" %}
  interface(COND_INTER) %{
    equal(0x1);
    not_equal(0x9);
    less(0xA);
    greater_equal(0x2);
    less_equal(0xB);
    greater(0x3);
  %}
%}

//----------OPERAND CLASSES----------------------------------------------------
// Operand Classes are groups of operands that are used to simplify
T
twisti 已提交
4311
// instruction definitions by not requiring the AD writer to specify separate
D
duke 已提交
4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336 4337 4338 4339 4340 4341 4342 4343 4344 4345 4346 4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375 4376 4377 4378 4379 4380 4381 4382 4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448 4449 4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488 4489 4490 4491 4492 4493 4494 4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599 4600 4601 4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612 4613 4614 4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648 4649 4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666 4667 4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691 4692 4693 4694 4695 4696 4697 4698 4699 4700 4701 4702 4703 4704 4705 4706 4707 4708 4709 4710 4711 4712 4713 4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725 4726 4727 4728 4729 4730 4731 4732 4733 4734 4735 4736 4737 4738 4739 4740 4741 4742 4743 4744 4745 4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758 4759 4760 4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774 4775 4776 4777 4778 4779 4780 4781 4782 4783 4784 4785 4786 4787 4788 4789 4790 4791 4792 4793 4794 4795 4796 4797 4798 4799 4800 4801 4802 4803 4804 4805 4806 4807 4808 4809 4810 4811 4812 4813 4814 4815 4816 4817 4818 4819 4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862 4863 4864 4865 4866 4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887 4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920 4921 4922 4923 4924 4925 4926 4927 4928 4929 4930 4931 4932 4933 4934 4935 4936 4937 4938 4939 4940 4941 4942 4943 4944 4945 4946 4947 4948 4949 4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977 4978 4979 4980 4981 4982 4983 4984 4985 4986 4987 4988 4989 4990 4991 4992 4993 4994 4995 4996 4997 4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063 5064 5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103 5104 5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197 5198 5199 5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217 5218 5219 5220 5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231 5232 5233 5234 5235 5236 5237 5238
// instructions for every form of operand when the instruction accepts
// multiple operand types with the same basic encoding and format.  The classic
// case of this is memory operands.
// Indirect is not included since its use is limited to Compare & Swap
opclass memory( indirect, indOffset13, indIndex );

//----------PIPELINE-----------------------------------------------------------
pipeline %{

//----------ATTRIBUTES---------------------------------------------------------
attributes %{
  fixed_size_instructions;           // Fixed size instructions
  branch_has_delay_slot;             // Branch has delay slot following
  max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
  instruction_unit_size = 4;         // An instruction is 4 bytes long
  instruction_fetch_unit_size = 16;  // The processor fetches one line
  instruction_fetch_units = 1;       // of 16 bytes

  // List of nop instructions
  nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
%}

//----------RESOURCES----------------------------------------------------------
// Resources are the functional units available to the machine
resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);

//----------PIPELINE DESCRIPTION-----------------------------------------------
// Pipeline Description specifies the stages in the machine's pipeline

pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);

//----------PIPELINE CLASSES---------------------------------------------------
// Pipeline Classes describe the stages in which input and output are
// referenced by the hardware pipeline.

// Integer ALU reg-reg operation
pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
    single_instruction;
    dst   : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU reg-reg long operation
pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
    instruction_count(2);
    dst   : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
    IALU  : R;
%}

// Integer ALU reg-reg long dependent operation
pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write);
    src1  : R(read);
    src2  : R(read);
    cr    : E(write);
    IALU  : R(2);
%}

// Integer ALU reg-imm operaion
pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
    single_instruction;
    dst   : E(write);
    src1  : R(read);
    IALU  : R;
%}

// Integer ALU reg-reg operation with condition code
pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
    single_instruction;
    dst   : E(write);
    cr    : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU reg-imm operation with condition code
pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
    single_instruction;
    dst   : E(write);
    cr    : E(write);
    src1  : R(read);
    IALU  : R;
%}

// Integer ALU zero-reg operation
pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
    single_instruction;
    dst   : E(write);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU zero-reg operation with condition code only
pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
    single_instruction;
    cr    : E(write);
    src   : R(read);
    IALU  : R;
%}

// Integer ALU reg-reg operation with condition code only
pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
    single_instruction;
    cr    : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU reg-imm operation with condition code only
pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
    single_instruction;
    cr    : E(write);
    src1  : R(read);
    IALU  : R;
%}

// Integer ALU reg-reg-zero operation with condition code only
pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
    single_instruction;
    cr    : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU reg-imm-zero operation with condition code only
pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
    single_instruction;
    cr    : E(write);
    src1  : R(read);
    IALU  : R;
%}

// Integer ALU reg-reg operation with condition code, src1 modified
pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
    single_instruction;
    cr    : E(write);
    src1  : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU reg-imm operation with condition code, src1 modified
pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
    single_instruction;
    cr    : E(write);
    src1  : E(write);
    src1  : R(read);
    IALU  : R;
%}

pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
    multiple_bundles;
    dst   : E(write)+4;
    cr    : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R(3);
    BR    : R(2);
%}

// Integer ALU operation
pipe_class ialu_none(iRegI dst) %{
    single_instruction;
    dst   : E(write);
    IALU  : R;
%}

// Integer ALU reg operation
pipe_class ialu_reg(iRegI dst, iRegI src) %{
    single_instruction; may_have_no_code;
    dst   : E(write);
    src   : R(read);
    IALU  : R;
%}

// Integer ALU reg conditional operation
// This instruction has a 1 cycle stall, and cannot execute
// in the same cycle as the instruction setting the condition
// code. We kludge this by pretending to read the condition code
// 1 cycle earlier, and by marking the functional units as busy
// for 2 cycles with the result available 1 cycle later than
// is really the case.
pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
    single_instruction;
    op2_out : C(write);
    op1     : R(read);
    cr      : R(read);       // This is really E, with a 1 cycle stall
    BR      : R(2);
    MS      : R(2);
%}

#ifdef _LP64
pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
    instruction_count(1); multiple_bundles;
    dst     : C(write)+1;
    src     : R(read)+1;
    IALU    : R(1);
    BR      : E(2);
    MS      : E(2);
%}
#endif

// Integer ALU reg operation
pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
    single_instruction; may_have_no_code;
    dst   : E(write);
    src   : R(read);
    IALU  : R;
%}
pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
    single_instruction; may_have_no_code;
    dst   : E(write);
    src   : R(read);
    IALU  : R;
%}

// Two integer ALU reg operations
pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
    instruction_count(2);
    dst   : E(write);
    src   : R(read);
    A0    : R;
    A1    : R;
%}

// Two integer ALU reg operations
pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
    instruction_count(2); may_have_no_code;
    dst   : E(write);
    src   : R(read);
    A0    : R;
    A1    : R;
%}

// Integer ALU imm operation
pipe_class ialu_imm(iRegI dst, immI13 src) %{
    single_instruction;
    dst   : E(write);
    IALU  : R;
%}

// Integer ALU reg-reg with carry operation
pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
    single_instruction;
    dst   : E(write);
    src1  : R(read);
    src2  : R(read);
    IALU  : R;
%}

// Integer ALU cc operation
pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
    single_instruction;
    dst   : E(write);
    cc    : R(read);
    IALU  : R;
%}

// Integer ALU cc / second IALU operation
pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write)+1;
    src   : R(read);
    IALU  : R;
%}

// Integer ALU cc / second IALU operation
pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write)+1;
    p     : R(read);
    q     : R(read);
    IALU  : R;
%}

// Integer ALU hi-lo-reg operation
pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write)+1;
    IALU  : R(2);
%}

// Float ALU hi-lo-reg operation (with temp)
pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write)+1;
    IALU  : R(2);
%}

// Long Constant
pipe_class loadConL( iRegL dst, immL src ) %{
    instruction_count(2); multiple_bundles;
    dst   : E(write)+1;
    IALU  : R(2);
    IALU  : R(2);
%}

// Pointer Constant
pipe_class loadConP( iRegP dst, immP src ) %{
    instruction_count(0); multiple_bundles;
    fixed_latency(6);
%}

// Polling Address
pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
#ifdef _LP64
    instruction_count(0); multiple_bundles;
    fixed_latency(6);
#else
    dst   : E(write);
    IALU  : R;
#endif
%}

// Long Constant small
pipe_class loadConLlo( iRegL dst, immL src ) %{
    instruction_count(2);
    dst   : E(write);
    IALU  : R;
    IALU  : R;
%}

// [PHH] This is wrong for 64-bit.  See LdImmF/D.
pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
    instruction_count(1); multiple_bundles;
    src   : R(read);
    dst   : M(write)+1;
    IALU  : R;
    MS    : E;
%}

// Integer ALU nop operation
pipe_class ialu_nop() %{
    single_instruction;
    IALU  : R;
%}

// Integer ALU nop operation
pipe_class ialu_nop_A0() %{
    single_instruction;
    A0    : R;
%}

// Integer ALU nop operation
pipe_class ialu_nop_A1() %{
    single_instruction;
    A1    : R;
%}

// Integer Multiply reg-reg operation
pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
    single_instruction;
    dst   : E(write);
    src1  : R(read);
    src2  : R(read);
    MS    : R(5);
%}

// Integer Multiply reg-imm operation
pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
    single_instruction;
    dst   : E(write);
    src1  : R(read);
    MS    : R(5);
%}

pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
    single_instruction;
    dst   : E(write)+4;
    src1  : R(read);
    src2  : R(read);
    MS    : R(6);
%}

pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
    single_instruction;
    dst   : E(write)+4;
    src1  : R(read);
    MS    : R(6);
%}

// Integer Divide reg-reg
pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write);
    temp  : E(write);
    src1  : R(read);
    src2  : R(read);
    temp  : R(read);
    MS    : R(38);
%}

// Integer Divide reg-imm
pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : E(write);
    temp  : E(write);
    src1  : R(read);
    temp  : R(read);
    MS    : R(38);
%}

// Long Divide
pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
    dst  : E(write)+71;
    src1 : R(read);
    src2 : R(read)+1;
    MS   : R(70);
%}

pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
    dst  : E(write)+71;
    src1 : R(read);
    MS   : R(70);
%}

// Floating Point Add Float
pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FA    : R;
%}

// Floating Point Add Double
pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FA    : R;
%}

// Floating Point Conditional Move based on integer flags
pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    cr    : R(read);
    FA    : R(2);
    BR    : R(2);
%}

// Floating Point Conditional Move based on integer flags
pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    cr    : R(read);
    FA    : R(2);
    BR    : R(2);
%}

// Floating Point Multiply Float
pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FM    : R;
%}

// Floating Point Multiply Double
pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FM    : R;
%}

// Floating Point Divide Float
pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FM    : R;
    FDIV  : C(14);
%}

// Floating Point Divide Double
pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
    single_instruction;
    dst   : X(write);
    src1  : E(read);
    src2  : E(read);
    FM    : R;
    FDIV  : C(17);
%}

// Floating Point Move/Negate/Abs Float
pipe_class faddF_reg(regF dst, regF src) %{
    single_instruction;
    dst   : W(write);
    src   : E(read);
    FA    : R(1);
%}

// Floating Point Move/Negate/Abs Double
pipe_class faddD_reg(regD dst, regD src) %{
    single_instruction;
    dst   : W(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert F->D
pipe_class fcvtF2D(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert I->D
pipe_class fcvtI2D(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert LHi->D
pipe_class fcvtLHi2D(regD dst, regD src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert L->D
pipe_class fcvtL2D(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert L->F
pipe_class fcvtL2F(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert D->F
pipe_class fcvtD2F(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert I->L
pipe_class fcvtI2L(regD dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert D->F
pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : X(write)+6;
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert D->L
pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : X(write)+6;
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert F->I
pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : X(write)+6;
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert F->L
pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
    instruction_count(1); multiple_bundles;
    dst   : X(write)+6;
    src   : E(read);
    FA    : R;
%}

// Floating Point Convert I->F
pipe_class fcvtI2F(regF dst, regF src) %{
    single_instruction;
    dst   : X(write);
    src   : E(read);
    FA    : R;
%}

// Floating Point Compare
pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
    single_instruction;
    cr    : X(write);
    src1  : E(read);
    src2  : E(read);
    FA    : R;
%}

// Floating Point Compare
pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
    single_instruction;
    cr    : X(write);
    src1  : E(read);
    src2  : E(read);
    FA    : R;
%}

// Floating Add Nop
pipe_class fadd_nop() %{
    single_instruction;
    FA  : R;
%}

// Integer Store to Memory
pipe_class istore_mem_reg(memory mem, iRegI src) %{
    single_instruction;
    mem   : R(read);
    src   : C(read);
    MS    : R;
%}

// Integer Store to Memory
pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
    single_instruction;
    mem   : R(read);
    src   : C(read);
    MS    : R;
%}

// Integer Store Zero to Memory
pipe_class istore_mem_zero(memory mem, immI0 src) %{
    single_instruction;
    mem   : R(read);
    MS    : R;
%}

// Special Stack Slot Store
pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
    single_instruction;
    stkSlot : R(read);
    src     : C(read);
    MS      : R;
%}

// Special Stack Slot Store
pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
    instruction_count(2); multiple_bundles;
    stkSlot : R(read);
    src     : C(read);
    MS      : R(2);
%}

// Float Store
pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
    single_instruction;
    mem : R(read);
    src : C(read);
    MS  : R;
%}

// Float Store
pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
    single_instruction;
    mem : R(read);
    MS  : R;
%}

// Double Store
pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
    instruction_count(1);
    mem : R(read);
    src : C(read);
    MS  : R;
%}

// Double Store
pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
    single_instruction;
    mem : R(read);
    MS  : R;
%}

// Special Stack Slot Float Store
pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
    single_instruction;
    stkSlot : R(read);
    src     : C(read);
    MS      : R;
%}

// Special Stack Slot Double Store
pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
    single_instruction;
    stkSlot : R(read);
    src     : C(read);
    MS      : R;
%}

// Integer Load (when sign bit propagation not needed)
pipe_class iload_mem(iRegI dst, memory mem) %{
    single_instruction;
    mem : R(read);
    dst : C(write);
    MS  : R;
%}

// Integer Load from stack operand
pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
    single_instruction;
    mem : R(read);
    dst : C(write);
    MS  : R;
%}

// Integer Load (when sign bit propagation or masking is needed)
pipe_class iload_mask_mem(iRegI dst, memory mem) %{
    single_instruction;
    mem : R(read);
    dst : M(write);
    MS  : R;
%}

// Float Load
pipe_class floadF_mem(regF dst, memory mem) %{
    single_instruction;
    mem : R(read);
    dst : M(write);
    MS  : R;
%}

// Float Load
pipe_class floadD_mem(regD dst, memory mem) %{
    instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
    mem : R(read);
    dst : M(write);
    MS  : R;
%}

// Float Load
pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
    single_instruction;
    stkSlot : R(read);
    dst : M(write);
    MS  : R;
%}

// Float Load
pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
    single_instruction;
    stkSlot : R(read);
    dst : M(write);
    MS  : R;
%}

// Memory Nop
pipe_class mem_nop() %{
    single_instruction;
    MS  : R;
%}

pipe_class sethi(iRegP dst, immI src) %{
    single_instruction;
    dst  : E(write);
    IALU : R;
%}

pipe_class loadPollP(iRegP poll) %{
    single_instruction;
    poll : R(read);
    MS   : R;
%}

pipe_class br(Universe br, label labl) %{
    single_instruction_with_delay_slot;
    BR  : R;
%}

pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
    single_instruction_with_delay_slot;
    cr    : E(read);
    BR    : R;
%}

pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
    single_instruction_with_delay_slot;
    op1 : E(read);
    BR  : R;
    MS  : R;
%}

pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
    single_instruction_with_delay_slot;
    cr    : E(read);
    BR    : R;
%}

pipe_class br_nop() %{
    single_instruction;
    BR  : R;
%}

pipe_class simple_call(method meth) %{
    instruction_count(2); multiple_bundles; force_serialization;
    fixed_latency(100);
    BR  : R(1);
    MS  : R(1);
    A0  : R(1);
%}

pipe_class compiled_call(method meth) %{
    instruction_count(1); multiple_bundles; force_serialization;
    fixed_latency(100);
    MS  : R(1);
%}

pipe_class call(method meth) %{
    instruction_count(0); multiple_bundles; force_serialization;
    fixed_latency(100);
%}

pipe_class tail_call(Universe ignore, label labl) %{
    single_instruction; has_delay_slot;
    fixed_latency(100);
    BR  : R(1);
    MS  : R(1);
%}

pipe_class ret(Universe ignore) %{
    single_instruction; has_delay_slot;
    BR  : R(1);
    MS  : R(1);
%}

pipe_class ret_poll(g3RegP poll) %{
    instruction_count(3); has_delay_slot;
    poll : E(read);
    MS   : R;
%}

// The real do-nothing guy
pipe_class empty( ) %{
    instruction_count(0);
%}

pipe_class long_memory_op() %{
    instruction_count(0); multiple_bundles; force_serialization;
    fixed_latency(25);
    MS  : R(1);
%}

// Check-cast
pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
    array : R(read);
    match  : R(read);
    IALU   : R(2);
    BR     : R(2);
    MS     : R;
%}

// Convert FPU flags into +1,0,-1
pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
    src1  : E(read);
    src2  : E(read);
    dst   : E(write);
    FA    : R;
    MS    : R(2);
    BR    : R(2);
%}

// Compare for p < q, and conditionally add y
pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
    p     : E(read);
    q     : E(read);
    y     : E(read);
    IALU  : R(3)
%}

// Perform a compare, then move conditionally in a branch delay slot.
pipe_class min_max( iRegI src2, iRegI srcdst ) %{
    src2   : E(read);
    srcdst : E(read);
    IALU   : R;
    BR     : R;
%}

// Define the class for the Nop node
define %{
   MachNop = ialu_nop;
%}

%}

//----------INSTRUCTIONS-------------------------------------------------------

//------------Special Stack Slot instructions - no match rules-----------------
instruct stkI_to_regF(regF dst, stackSlotI src) %{
  // No match rule to avoid chain rule match.
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDF    $src,$dst\t! stkI to regF" %}
  opcode(Assembler::ldf_op3);
5239
  ins_encode(simple_form3_mem_reg(src, dst));
D
duke 已提交
5240 5241 5242 5243 5244 5245 5246 5247 5248 5249
  ins_pipe(floadF_stk);
%}

instruct stkL_to_regD(regD dst, stackSlotL src) %{
  // No match rule to avoid chain rule match.
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDDF   $src,$dst\t! stkL to regD" %}
  opcode(Assembler::lddf_op3);
5250
  ins_encode(simple_form3_mem_reg(src, dst));
D
duke 已提交
5251 5252 5253 5254 5255 5256 5257 5258 5259 5260
  ins_pipe(floadD_stk);
%}

instruct regF_to_stkI(stackSlotI dst, regF src) %{
  // No match rule to avoid chain rule match.
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STF    $src,$dst\t! regF to stkI" %}
  opcode(Assembler::stf_op3);
5261
  ins_encode(simple_form3_mem_reg(dst, src));
D
duke 已提交
5262 5263 5264 5265 5266 5267 5268 5269 5270 5271
  ins_pipe(fstoreF_stk_reg);
%}

instruct regD_to_stkL(stackSlotL dst, regD src) %{
  // No match rule to avoid chain rule match.
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STDF   $src,$dst\t! regD to stkL" %}
  opcode(Assembler::stdf_op3);
5272
  ins_encode(simple_form3_mem_reg(dst, src));
D
duke 已提交
5273 5274 5275 5276 5277 5278 5279 5280 5281 5282
  ins_pipe(fstoreD_stk_reg);
%}

instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST*2);
  size(8);
  format %{ "STW    $src,$dst.hi\t! long\n\t"
            "STW    R_G0,$dst.lo" %}
  opcode(Assembler::stw_op3);
5283
  ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
D
duke 已提交
5284 5285 5286 5287 5288 5289 5290 5291 5292 5293
  ins_pipe(lstoreI_stk_reg);
%}

instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
  // No match rule to avoid chain rule match.
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $src,$dst\t! regL to stkD" %}
  opcode(Assembler::stx_op3);
5294
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
5295 5296 5297 5298 5299 5300 5301 5302 5303 5304 5305 5306 5307
  ins_pipe(istore_stk_reg);
%}

//---------- Chain stack slots between similar types --------

// Load integer from stack slot
instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDUW   $src,$dst\t!stk" %}
  opcode(Assembler::lduw_op3);
5308
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
5309 5310 5311 5312 5313 5314 5315 5316 5317 5318 5319
  ins_pipe(iload_mem);
%}

// Store integer to stack slot
instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STW    $src,$dst\t!stk" %}
  opcode(Assembler::stw_op3);
5320
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
5321 5322 5323 5324 5325 5326 5327 5328 5329 5330 5331
  ins_pipe(istore_mem_reg);
%}

// Load long from stack slot
instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
  match(Set dst src);

  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDX    $src,$dst\t! long" %}
  opcode(Assembler::ldx_op3);
5332
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
5333 5334 5335 5336 5337 5338 5339 5340 5341 5342 5343
  ins_pipe(iload_mem);
%}

// Store long to stack slot
instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
  match(Set dst src);

  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $src,$dst\t! long" %}
  opcode(Assembler::stx_op3);
5344
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
5345 5346 5347 5348 5349 5350 5351 5352 5353 5354 5355
  ins_pipe(istore_mem_reg);
%}

#ifdef _LP64
// Load pointer from stack slot, 64-bit encoding
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDX    $src,$dst\t!ptr" %}
  opcode(Assembler::ldx_op3);
5356
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
5357 5358 5359 5360 5361 5362 5363 5364 5365 5366
  ins_pipe(iload_mem);
%}

// Store pointer to stack slot
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $src,$dst\t!ptr" %}
  opcode(Assembler::stx_op3);
5367
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
5368 5369 5370 5371 5372 5373 5374 5375 5376
  ins_pipe(istore_mem_reg);
%}
#else // _LP64
// Load pointer from stack slot, 32-bit encoding
instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);
  format %{ "LDUW   $src,$dst\t!ptr" %}
  opcode(Assembler::lduw_op3, Assembler::ldst_op);
5377
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
5378 5379 5380 5381 5382 5383 5384 5385 5386
  ins_pipe(iload_mem);
%}

// Store pointer to stack slot
instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
  match(Set dst src);
  ins_cost(MEMORY_REF_COST);
  format %{ "STW    $src,$dst\t!ptr" %}
  opcode(Assembler::stw_op3, Assembler::ldst_op);
5387
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
5388 5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415 5416 5417 5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435 5436 5437 5438 5439 5440 5441 5442 5443 5444 5445 5446 5447
  ins_pipe(istore_mem_reg);
%}
#endif // _LP64

//------------Special Nop instructions for bundling - no match rules-----------
// Nop using the A0 functional unit
instruct Nop_A0() %{
  ins_cost(0);

  format %{ "NOP    ! Alu Pipeline" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form2_nop() );
  ins_pipe(ialu_nop_A0);
%}

// Nop using the A1 functional unit
instruct Nop_A1( ) %{
  ins_cost(0);

  format %{ "NOP    ! Alu Pipeline" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form2_nop() );
  ins_pipe(ialu_nop_A1);
%}

// Nop using the memory functional unit
instruct Nop_MS( ) %{
  ins_cost(0);

  format %{ "NOP    ! Memory Pipeline" %}
  ins_encode( emit_mem_nop );
  ins_pipe(mem_nop);
%}

// Nop using the floating add functional unit
instruct Nop_FA( ) %{
  ins_cost(0);

  format %{ "NOP    ! Floating Add Pipeline" %}
  ins_encode( emit_fadd_nop );
  ins_pipe(fadd_nop);
%}

// Nop using the branch functional unit
instruct Nop_BR( ) %{
  ins_cost(0);

  format %{ "NOP    ! Branch Pipeline" %}
  ins_encode( emit_br_nop );
  ins_pipe(br_nop);
%}

//----------Load/Store/Move Instructions---------------------------------------
//----------Load Instructions--------------------------------------------------
// Load Byte (8bit signed)
instruct loadB(iRegI dst, memory mem) %{
  match(Set dst (LoadB mem));
  ins_cost(MEMORY_REF_COST);

  size(4);
5448
  format %{ "LDSB   $mem,$dst\t! byte" %}
5449 5450 5451
  ins_encode %{
    __ ldsb($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5452 5453 5454
  ins_pipe(iload_mask_mem);
%}

5455 5456 5457
// Load Byte (8bit signed) into a Long Register
instruct loadB2L(iRegL dst, memory mem) %{
  match(Set dst (ConvI2L (LoadB mem)));
D
duke 已提交
5458 5459 5460
  ins_cost(MEMORY_REF_COST);

  size(4);
5461
  format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5462 5463 5464
  ins_encode %{
    __ ldsb($mem$$Address, $dst$$Register);
  %}
5465 5466 5467 5468 5469 5470 5471 5472 5473 5474
  ins_pipe(iload_mask_mem);
%}

// Load Unsigned Byte (8bit UNsigned) into an int reg
instruct loadUB(iRegI dst, memory mem) %{
  match(Set dst (LoadUB mem));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDUB   $mem,$dst\t! ubyte" %}
5475 5476 5477
  ins_encode %{
    __ ldub($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5478 5479 5480
  ins_pipe(iload_mask_mem);
%}

5481 5482 5483
// Load Unsigned Byte (8bit UNsigned) into a Long Register
instruct loadUB2L(iRegL dst, memory mem) %{
  match(Set dst (ConvI2L (LoadUB mem)));
D
duke 已提交
5484 5485 5486
  ins_cost(MEMORY_REF_COST);

  size(4);
5487
  format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5488 5489 5490
  ins_encode %{
    __ ldub($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5491 5492 5493
  ins_pipe(iload_mask_mem);
%}

5494 5495 5496
// Load Short (16bit signed)
instruct loadS(iRegI dst, memory mem) %{
  match(Set dst (LoadS mem));
D
duke 已提交
5497 5498 5499
  ins_cost(MEMORY_REF_COST);

  size(4);
5500
  format %{ "LDSH   $mem,$dst\t! short" %}
5501 5502 5503
  ins_encode %{
    __ ldsh($mem$$Address, $dst$$Register);
  %}
5504 5505 5506 5507 5508 5509 5510 5511 5512 5513
  ins_pipe(iload_mask_mem);
%}

// Load Short (16bit signed) into a Long Register
instruct loadS2L(iRegL dst, memory mem) %{
  match(Set dst (ConvI2L (LoadS mem)));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDSH   $mem,$dst\t! short -> long" %}
5514 5515 5516
  ins_encode %{
    __ ldsh($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5517 5518 5519
  ins_pipe(iload_mask_mem);
%}

5520
// Load Unsigned Short/Char (16bit UNsigned)
5521 5522
instruct loadUS(iRegI dst, memory mem) %{
  match(Set dst (LoadUS mem));
D
duke 已提交
5523 5524 5525
  ins_cost(MEMORY_REF_COST);

  size(4);
5526
  format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5527 5528 5529
  ins_encode %{
    __ lduh($mem$$Address, $dst$$Register);
  %}
5530 5531 5532 5533 5534 5535 5536 5537 5538 5539
  ins_pipe(iload_mask_mem);
%}

// Load Unsigned Short/Char (16bit UNsigned) into a Long Register
instruct loadUS2L(iRegL dst, memory mem) %{
  match(Set dst (ConvI2L (LoadUS mem)));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5540 5541 5542
  ins_encode %{
    __ lduh($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5543 5544 5545 5546 5547 5548 5549
  ins_pipe(iload_mask_mem);
%}

// Load Integer
instruct loadI(iRegI dst, memory mem) %{
  match(Set dst (LoadI mem));
  ins_cost(MEMORY_REF_COST);
5550

D
duke 已提交
5551
  size(4);
5552
  format %{ "LDUW   $mem,$dst\t! int" %}
5553 5554 5555
  ins_encode %{
    __ lduw($mem$$Address, $dst$$Register);
  %}
5556 5557 5558 5559 5560 5561 5562 5563 5564 5565
  ins_pipe(iload_mem);
%}

// Load Integer into a Long Register
instruct loadI2L(iRegL dst, memory mem) %{
  match(Set dst (ConvI2L (LoadI mem)));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDSW   $mem,$dst\t! int -> long" %}
5566 5567 5568
  ins_encode %{
    __ ldsw($mem$$Address, $dst$$Register);
  %}
5569 5570 5571 5572 5573 5574 5575
  ins_pipe(iload_mem);
%}

// Load Unsigned Integer into a Long Register
instruct loadUI2L(iRegL dst, memory mem) %{
  match(Set dst (LoadUI2L mem));
  ins_cost(MEMORY_REF_COST);
D
duke 已提交
5576

5577 5578
  size(4);
  format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5579 5580 5581
  ins_encode %{
    __ lduw($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5582 5583 5584 5585 5586 5587 5588
  ins_pipe(iload_mem);
%}

// Load Long - aligned
instruct loadL(iRegL dst, memory mem ) %{
  match(Set dst (LoadL mem));
  ins_cost(MEMORY_REF_COST);
5589

D
duke 已提交
5590 5591
  size(4);
  format %{ "LDX    $mem,$dst\t! long" %}
5592 5593 5594
  ins_encode %{
    __ ldx($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5595 5596 5597 5598 5599 5600 5601 5602 5603 5604 5605 5606 5607 5608
  ins_pipe(iload_mem);
%}

// Load Long - UNaligned
instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
  match(Set dst (LoadL_unaligned mem));
  effect(KILL tmp);
  ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
  size(16);
  format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
          "\tLDUW   $mem  ,$dst\n"
          "\tSLLX   #32, $dst, $dst\n"
          "\tOR     $dst, R_O7, $dst" %}
  opcode(Assembler::lduw_op3);
5609
  ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
D
duke 已提交
5610 5611 5612 5613 5614 5615 5616 5617 5618 5619
  ins_pipe(iload_mem);
%}

// Load Aligned Packed Byte into a Double Register
instruct loadA8B(regD dst, memory mem) %{
  match(Set dst (Load8B mem));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDDF   $mem,$dst\t! packed8B" %}
  opcode(Assembler::lddf_op3);
5620
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5621 5622 5623 5624 5625 5626 5627 5628 5629 5630
  ins_pipe(floadD_mem);
%}

// Load Aligned Packed Char into a Double Register
instruct loadA4C(regD dst, memory mem) %{
  match(Set dst (Load4C mem));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDDF   $mem,$dst\t! packed4C" %}
  opcode(Assembler::lddf_op3);
5631
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5632 5633 5634 5635 5636 5637 5638 5639 5640 5641
  ins_pipe(floadD_mem);
%}

// Load Aligned Packed Short into a Double Register
instruct loadA4S(regD dst, memory mem) %{
  match(Set dst (Load4S mem));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDDF   $mem,$dst\t! packed4S" %}
  opcode(Assembler::lddf_op3);
5642
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5643 5644 5645 5646 5647 5648 5649 5650 5651 5652
  ins_pipe(floadD_mem);
%}

// Load Aligned Packed Int into a Double Register
instruct loadA2I(regD dst, memory mem) %{
  match(Set dst (Load2I mem));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDDF   $mem,$dst\t! packed2I" %}
  opcode(Assembler::lddf_op3);
5653
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5654 5655 5656 5657 5658 5659 5660 5661 5662 5663 5664
  ins_pipe(floadD_mem);
%}

// Load Range
instruct loadRange(iRegI dst, memory mem) %{
  match(Set dst (LoadRange mem));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDUW   $mem,$dst\t! range" %}
  opcode(Assembler::lduw_op3);
5665
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5666 5667 5668 5669 5670 5671 5672 5673 5674 5675 5676
  ins_pipe(iload_mem);
%}

// Load Integer into %f register (for fitos/fitod)
instruct loadI_freg(regF dst, memory mem) %{
  match(Set dst (LoadI mem));
  ins_cost(MEMORY_REF_COST);
  size(4);

  format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
  opcode(Assembler::ldf_op3);
5677
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5678 5679 5680 5681 5682 5683 5684 5685 5686 5687 5688
  ins_pipe(floadF_mem);
%}

// Load Pointer
instruct loadP(iRegP dst, memory mem) %{
  match(Set dst (LoadP mem));
  ins_cost(MEMORY_REF_COST);
  size(4);

#ifndef _LP64
  format %{ "LDUW   $mem,$dst\t! ptr" %}
5689 5690 5691
  ins_encode %{
    __ lduw($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5692 5693
#else
  format %{ "LDX    $mem,$dst\t! ptr" %}
5694 5695 5696
  ins_encode %{
    __ ldx($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5697 5698 5699 5700
#endif
  ins_pipe(iload_mem);
%}

5701 5702
// Load Compressed Pointer
instruct loadN(iRegN dst, memory mem) %{
5703 5704 5705 5706 5707 5708 5709 5710 5711
  match(Set dst (LoadN mem));
  ins_cost(MEMORY_REF_COST);
  size(4);

  format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
  ins_encode %{
    __ lduw($mem$$Address, $dst$$Register);
  %}
  ins_pipe(iload_mem);
5712 5713
%}

D
duke 已提交
5714 5715 5716 5717 5718 5719 5720 5721
// Load Klass Pointer
instruct loadKlass(iRegP dst, memory mem) %{
  match(Set dst (LoadKlass mem));
  ins_cost(MEMORY_REF_COST);
  size(4);

#ifndef _LP64
  format %{ "LDUW   $mem,$dst\t! klass ptr" %}
5722 5723 5724
  ins_encode %{
    __ lduw($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5725 5726
#else
  format %{ "LDX    $mem,$dst\t! klass ptr" %}
5727 5728 5729
  ins_encode %{
    __ ldx($mem$$Address, $dst$$Register);
  %}
D
duke 已提交
5730 5731 5732 5733
#endif
  ins_pipe(iload_mem);
%}

5734 5735 5736
// Load narrow Klass Pointer
instruct loadNKlass(iRegN dst, memory mem) %{
  match(Set dst (LoadNKlass mem));
5737
  ins_cost(MEMORY_REF_COST);
5738
  size(4);
5739 5740 5741

  format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
  ins_encode %{
5742
    __ lduw($mem$$Address, $dst$$Register);
5743 5744 5745 5746
  %}
  ins_pipe(iload_mem);
%}

D
duke 已提交
5747 5748 5749 5750 5751 5752 5753 5754
// Load Double
instruct loadD(regD dst, memory mem) %{
  match(Set dst (LoadD mem));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDDF   $mem,$dst" %}
  opcode(Assembler::lddf_op3);
5755
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5756 5757 5758 5759 5760 5761 5762 5763 5764 5765 5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778
  ins_pipe(floadD_mem);
%}

// Load Double - UNaligned
instruct loadD_unaligned(regD_low dst, memory mem ) %{
  match(Set dst (LoadD_unaligned mem));
  ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
  size(8);
  format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
          "\tLDF    $mem+4,$dst.lo\t!" %}
  opcode(Assembler::ldf_op3);
  ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
  ins_pipe(iload_mem);
%}

// Load Float
instruct loadF(regF dst, memory mem) %{
  match(Set dst (LoadF mem));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDF    $mem,$dst" %}
  opcode(Assembler::ldf_op3);
5779
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
5780 5781 5782 5783 5784 5785 5786 5787 5788 5789 5790 5791 5792 5793 5794 5795 5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808 5809 5810 5811 5812 5813 5814 5815 5816 5817 5818 5819 5820 5821 5822 5823 5824 5825 5826 5827
  ins_pipe(floadF_mem);
%}

// Load Constant
instruct loadConI( iRegI dst, immI src ) %{
  match(Set dst src);
  ins_cost(DEFAULT_COST * 3/2);
  format %{ "SET    $src,$dst" %}
  ins_encode( Set32(src, dst) );
  ins_pipe(ialu_hi_lo_reg);
%}

instruct loadConI13( iRegI dst, immI13 src ) %{
  match(Set dst src);

  size(4);
  format %{ "MOV    $src,$dst" %}
  ins_encode( Set13( src, dst ) );
  ins_pipe(ialu_imm);
%}

instruct loadConP(iRegP dst, immP src) %{
  match(Set dst src);
  ins_cost(DEFAULT_COST * 3/2);
  format %{ "SET    $src,$dst\t!ptr" %}
  // This rule does not use "expand" unlike loadConI because then
  // the result type is not known to be an Oop.  An ADLC
  // enhancement will be needed to make that work - not worth it!

  ins_encode( SetPtr( src, dst ) );
  ins_pipe(loadConP);

%}

instruct loadConP0(iRegP dst, immP0 src) %{
  match(Set dst src);

  size(4);
  format %{ "CLR    $dst\t!ptr" %}
  ins_encode( SetNull( dst ) );
  ins_pipe(ialu_imm);
%}

instruct loadConP_poll(iRegP dst, immP_poll src) %{
  match(Set dst src);
  ins_cost(DEFAULT_COST);
  format %{ "SET    $src,$dst\t!ptr" %}
  ins_encode %{
5828 5829
    AddressLiteral polling_page(os::get_polling_page());
    __ sethi(polling_page, reg_to_register_object($dst$$reg));
D
duke 已提交
5830 5831 5832 5833
  %}
  ins_pipe(loadConP_poll);
%}

5834 5835 5836 5837 5838 5839 5840 5841 5842
instruct loadConN0(iRegN dst, immN0 src) %{
  match(Set dst src);

  size(4);
  format %{ "CLR    $dst\t! compressed NULL ptr" %}
  ins_encode( SetNull( dst ) );
  ins_pipe(ialu_imm);
%}

5843 5844
instruct loadConN(iRegN dst, immN src) %{
  match(Set dst src);
5845 5846
  ins_cost(DEFAULT_COST * 3/2);
  format %{ "SET    $src,$dst\t! compressed ptr" %}
5847 5848
  ins_encode %{
    Register dst = $dst$$Register;
5849
    __ set_narrow_oop((jobject)$src$$constant, dst);
5850
  %}
5851
  ins_pipe(ialu_hi_lo_reg);
5852 5853
%}

D
duke 已提交
5854 5855 5856 5857 5858 5859 5860 5861 5862 5863 5864 5865 5866 5867 5868 5869 5870 5871 5872 5873 5874 5875 5876 5877 5878 5879 5880 5881 5882 5883 5884 5885 5886 5887
instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{
  // %%% maybe this should work like loadConD
  match(Set dst src);
  effect(KILL tmp);
  ins_cost(DEFAULT_COST * 4);
  format %{ "SET64   $src,$dst KILL $tmp\t! long" %}
  ins_encode( LdImmL(src, dst, tmp) );
  ins_pipe(loadConL);
%}

instruct loadConL0( iRegL dst, immL0 src ) %{
  match(Set dst src);
  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "CLR    $dst\t! long" %}
  ins_encode( Set13( src, dst ) );
  ins_pipe(ialu_imm);
%}

instruct loadConL13( iRegL dst, immL13 src ) %{
  match(Set dst src);
  ins_cost(DEFAULT_COST * 2);

  size(4);
  format %{ "MOV    $src,$dst\t! long" %}
  ins_encode( Set13( src, dst ) );
  ins_pipe(ialu_imm);
%}

instruct loadConF(regF dst, immF src, o7RegP tmp) %{
  match(Set dst src);
  effect(KILL tmp);

#ifdef _LP64
5888
  size(8*4);
D
duke 已提交
5889
#else
5890
  size(2*4);
D
duke 已提交
5891 5892 5893 5894
#endif

  format %{ "SETHI  hi(&$src),$tmp\t!get float $src from table\n\t"
            "LDF    [$tmp+lo(&$src)],$dst" %}
5895 5896 5897 5898 5899 5900 5901 5902
  ins_encode %{
    address float_address = __ float_constant($src$$constant);
    RelocationHolder rspec = internal_word_Relocation::spec(float_address);
    AddressLiteral addrlit(float_address, rspec);

    __ sethi(addrlit, $tmp$$Register);
    __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
  %}
D
duke 已提交
5903 5904 5905 5906 5907 5908 5909 5910
  ins_pipe(loadConFD);
%}

instruct loadConD(regD dst, immD src, o7RegP tmp) %{
  match(Set dst src);
  effect(KILL tmp);

#ifdef _LP64
5911
  size(8*4);
D
duke 已提交
5912
#else
5913
  size(2*4);
D
duke 已提交
5914 5915 5916 5917
#endif

  format %{ "SETHI  hi(&$src),$tmp\t!get double $src from table\n\t"
            "LDDF   [$tmp+lo(&$src)],$dst" %}
5918 5919 5920 5921 5922 5923
  ins_encode %{
    address double_address = __ double_constant($src$$constant);
    RelocationHolder rspec = internal_word_Relocation::spec(double_address);
    AddressLiteral addrlit(double_address, rspec);

    __ sethi(addrlit, $tmp$$Register);
5924 5925 5926
    // XXX This is a quick fix for 6833573.
    //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec);
    __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec);
5927
  %}
D
duke 已提交
5928 5929 5930 5931 5932 5933 5934 5935 5936 5937 5938 5939 5940 5941 5942 5943 5944 5945 5946 5947 5948 5949 5950 5951 5952 5953 5954 5955 5956 5957 5958 5959 5960 5961 5962 5963
  ins_pipe(loadConFD);
%}

// Prefetch instructions.
// Must be safe to execute with invalid address (cannot fault).

instruct prefetchr( memory mem ) %{
  match( PrefetchRead mem );
  ins_cost(MEMORY_REF_COST);

  format %{ "PREFETCH $mem,0\t! Prefetch read-many" %}
  opcode(Assembler::prefetch_op3);
  ins_encode( form3_mem_prefetch_read( mem ) );
  ins_pipe(iload_mem);
%}

instruct prefetchw( memory mem ) %{
  match( PrefetchWrite mem );
  ins_cost(MEMORY_REF_COST);

  format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %}
  opcode(Assembler::prefetch_op3);
  ins_encode( form3_mem_prefetch_write( mem ) );
  ins_pipe(iload_mem);
%}


//----------Store Instructions-------------------------------------------------
// Store Byte
instruct storeB(memory mem, iRegI src) %{
  match(Set mem (StoreB mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STB    $src,$mem\t! byte" %}
  opcode(Assembler::stb_op3);
5964
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
5965 5966 5967 5968 5969 5970 5971 5972 5973 5974
  ins_pipe(istore_mem_reg);
%}

instruct storeB0(memory mem, immI0 src) %{
  match(Set mem (StoreB mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STB    $src,$mem\t! byte" %}
  opcode(Assembler::stb_op3);
5975
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
5976 5977 5978 5979 5980 5981 5982 5983 5984 5985
  ins_pipe(istore_mem_zero);
%}

instruct storeCM0(memory mem, immI0 src) %{
  match(Set mem (StoreCM mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
  opcode(Assembler::stb_op3);
5986
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
5987 5988 5989 5990 5991 5992 5993 5994 5995 5996 5997
  ins_pipe(istore_mem_zero);
%}

// Store Char/Short
instruct storeC(memory mem, iRegI src) %{
  match(Set mem (StoreC mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STH    $src,$mem\t! short" %}
  opcode(Assembler::sth_op3);
5998
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
5999 6000 6001 6002 6003 6004 6005 6006 6007 6008
  ins_pipe(istore_mem_reg);
%}

instruct storeC0(memory mem, immI0 src) %{
  match(Set mem (StoreC mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STH    $src,$mem\t! short" %}
  opcode(Assembler::sth_op3);
6009
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020
  ins_pipe(istore_mem_zero);
%}

// Store Integer
instruct storeI(memory mem, iRegI src) %{
  match(Set mem (StoreI mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STW    $src,$mem" %}
  opcode(Assembler::stw_op3);
6021
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6022 6023 6024 6025 6026 6027 6028 6029 6030 6031
  ins_pipe(istore_mem_reg);
%}

// Store Long
instruct storeL(memory mem, iRegL src) %{
  match(Set mem (StoreL mem src));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $src,$mem\t! long" %}
  opcode(Assembler::stx_op3);
6032
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6033 6034 6035 6036 6037 6038 6039 6040 6041 6042
  ins_pipe(istore_mem_reg);
%}

instruct storeI0(memory mem, immI0 src) %{
  match(Set mem (StoreI mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STW    $src,$mem" %}
  opcode(Assembler::stw_op3);
6043
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6044 6045 6046 6047 6048 6049 6050 6051 6052 6053
  ins_pipe(istore_mem_zero);
%}

instruct storeL0(memory mem, immL0 src) %{
  match(Set mem (StoreL mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STX    $src,$mem" %}
  opcode(Assembler::stx_op3);
6054
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065
  ins_pipe(istore_mem_zero);
%}

// Store Integer from float register (used after fstoi)
instruct storeI_Freg(memory mem, regF src) %{
  match(Set mem (StoreI mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
  opcode(Assembler::stf_op3);
6066
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6067 6068 6069 6070 6071 6072 6073 6074 6075 6076 6077 6078 6079 6080 6081 6082 6083 6084 6085 6086 6087 6088 6089 6090 6091 6092 6093 6094 6095 6096 6097 6098 6099 6100 6101 6102
  ins_pipe(fstoreF_mem_reg);
%}

// Store Pointer
instruct storeP(memory dst, sp_ptr_RegP src) %{
  match(Set dst (StoreP dst src));
  ins_cost(MEMORY_REF_COST);
  size(4);

#ifndef _LP64
  format %{ "STW    $src,$dst\t! ptr" %}
  opcode(Assembler::stw_op3, 0, REGP_OP);
#else
  format %{ "STX    $src,$dst\t! ptr" %}
  opcode(Assembler::stx_op3, 0, REGP_OP);
#endif
  ins_encode( form3_mem_reg( dst, src ) );
  ins_pipe(istore_mem_spORreg);
%}

instruct storeP0(memory dst, immP0 src) %{
  match(Set dst (StoreP dst src));
  ins_cost(MEMORY_REF_COST);
  size(4);

#ifndef _LP64
  format %{ "STW    $src,$dst\t! ptr" %}
  opcode(Assembler::stw_op3, 0, REGP_OP);
#else
  format %{ "STX    $src,$dst\t! ptr" %}
  opcode(Assembler::stx_op3, 0, REGP_OP);
#endif
  ins_encode( form3_mem_reg( dst, R_G0 ) );
  ins_pipe(istore_mem_zero);
%}

6103 6104 6105 6106 6107 6108 6109 6110 6111 6112 6113 6114 6115 6116 6117 6118 6119 6120 6121 6122 6123 6124 6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140
// Store Compressed Pointer
instruct storeN(memory dst, iRegN src) %{
   match(Set dst (StoreN dst src));
   ins_cost(MEMORY_REF_COST);
   size(4);

   format %{ "STW    $src,$dst\t! compressed ptr" %}
   ins_encode %{
     Register base = as_Register($dst$$base);
     Register index = as_Register($dst$$index);
     Register src = $src$$Register;
     if (index != G0) {
       __ stw(src, base, index);
     } else {
       __ stw(src, base, $dst$$disp);
     }
   %}
   ins_pipe(istore_mem_spORreg);
%}

instruct storeN0(memory dst, immN0 src) %{
   match(Set dst (StoreN dst src));
   ins_cost(MEMORY_REF_COST);
   size(4);

   format %{ "STW    $src,$dst\t! compressed ptr" %}
   ins_encode %{
     Register base = as_Register($dst$$base);
     Register index = as_Register($dst$$index);
     if (index != G0) {
       __ stw(0, base, index);
     } else {
       __ stw(0, base, $dst$$disp);
     }
   %}
   ins_pipe(istore_mem_zero);
%}

D
duke 已提交
6141 6142 6143 6144 6145 6146 6147 6148
// Store Double
instruct storeD( memory mem, regD src) %{
  match(Set mem (StoreD mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STDF   $src,$mem" %}
  opcode(Assembler::stdf_op3);
6149
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6150 6151 6152 6153 6154 6155 6156 6157 6158 6159
  ins_pipe(fstoreD_mem_reg);
%}

instruct storeD0( memory mem, immD0 src) %{
  match(Set mem (StoreD mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STX    $src,$mem" %}
  opcode(Assembler::stx_op3);
6160
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6161 6162 6163 6164 6165 6166 6167 6168 6169 6170 6171
  ins_pipe(fstoreD_mem_zero);
%}

// Store Float
instruct storeF( memory mem, regF src) %{
  match(Set mem (StoreF mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STF    $src,$mem" %}
  opcode(Assembler::stf_op3);
6172
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6173 6174 6175 6176 6177 6178 6179 6180 6181 6182
  ins_pipe(fstoreF_mem_reg);
%}

instruct storeF0( memory mem, immF0 src) %{
  match(Set mem (StoreF mem src));
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STW    $src,$mem\t! storeF0" %}
  opcode(Assembler::stw_op3);
6183
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6184 6185 6186 6187 6188 6189 6190 6191 6192 6193
  ins_pipe(fstoreF_mem_zero);
%}

// Store Aligned Packed Bytes in Double register to memory
instruct storeA8B(memory mem, regD src) %{
  match(Set mem (Store8B mem src));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STDF   $src,$mem\t! packed8B" %}
  opcode(Assembler::stdf_op3);
6194
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6195 6196 6197
  ins_pipe(fstoreD_mem_reg);
%}

6198 6199
// Convert oop pointer into compressed form
instruct encodeHeapOop(iRegN dst, iRegP src) %{
6200
  predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6201
  match(Set dst (EncodeP src));
6202
  format %{ "encode_heap_oop $src, $dst" %}
6203 6204 6205 6206 6207 6208
  ins_encode %{
    __ encode_heap_oop($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}

6209
instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6210
  predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6211 6212 6213 6214 6215 6216 6217 6218
  match(Set dst (EncodeP src));
  format %{ "encode_heap_oop_not_null $src, $dst" %}
  ins_encode %{
    __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}

6219
instruct decodeHeapOop(iRegP dst, iRegN src) %{
6220 6221
  predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
            n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6222 6223 6224 6225 6226 6227 6228 6229
  match(Set dst (DecodeN src));
  format %{ "decode_heap_oop $src, $dst" %}
  ins_encode %{
    __ decode_heap_oop($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}

6230
instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6231 6232
  predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
            n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6233 6234 6235 6236 6237 6238 6239 6240
  match(Set dst (DecodeN src));
  format %{ "decode_heap_oop_not_null $src, $dst" %}
  ins_encode %{
    __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}

6241

D
duke 已提交
6242 6243 6244 6245 6246 6247 6248
// Store Zero into Aligned Packed Bytes
instruct storeA8B0(memory mem, immI0 zero) %{
  match(Set mem (Store8B mem zero));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $zero,$mem\t! packed8B" %}
  opcode(Assembler::stx_op3);
6249
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6250 6251 6252 6253 6254 6255 6256 6257 6258 6259
  ins_pipe(fstoreD_mem_zero);
%}

// Store Aligned Packed Chars/Shorts in Double register to memory
instruct storeA4C(memory mem, regD src) %{
  match(Set mem (Store4C mem src));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STDF   $src,$mem\t! packed4C" %}
  opcode(Assembler::stdf_op3);
6260
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6261 6262 6263 6264 6265 6266 6267 6268 6269 6270
  ins_pipe(fstoreD_mem_reg);
%}

// Store Zero into Aligned Packed Chars/Shorts
instruct storeA4C0(memory mem, immI0 zero) %{
  match(Set mem (Store4C mem (Replicate4C zero)));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $zero,$mem\t! packed4C" %}
  opcode(Assembler::stx_op3);
6271
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6272 6273 6274 6275 6276 6277 6278 6279 6280 6281
  ins_pipe(fstoreD_mem_zero);
%}

// Store Aligned Packed Ints in Double register to memory
instruct storeA2I(memory mem, regD src) %{
  match(Set mem (Store2I mem src));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STDF   $src,$mem\t! packed2I" %}
  opcode(Assembler::stdf_op3);
6282
  ins_encode(simple_form3_mem_reg( mem, src ) );
D
duke 已提交
6283 6284 6285 6286 6287 6288 6289 6290 6291 6292
  ins_pipe(fstoreD_mem_reg);
%}

// Store Zero into Aligned Packed Ints
instruct storeA2I0(memory mem, immI0 zero) %{
  match(Set mem (Store2I mem zero));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "STX    $zero,$mem\t! packed2I" %}
  opcode(Assembler::stx_op3);
6293
  ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
D
duke 已提交
6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319 6320 6321 6322 6323 6324 6325 6326 6327 6328 6329 6330 6331 6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344 6345 6346 6347 6348 6349 6350 6351 6352 6353 6354 6355 6356 6357 6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370 6371 6372 6373 6374 6375 6376 6377 6378 6379 6380 6381 6382 6383 6384 6385 6386 6387 6388 6389 6390 6391 6392 6393 6394 6395 6396 6397 6398 6399 6400 6401 6402 6403 6404 6405 6406
  ins_pipe(fstoreD_mem_zero);
%}


//----------MemBar Instructions-----------------------------------------------
// Memory barrier flavors

instruct membar_acquire() %{
  match(MemBarAcquire);
  ins_cost(4*MEMORY_REF_COST);

  size(0);
  format %{ "MEMBAR-acquire" %}
  ins_encode( enc_membar_acquire );
  ins_pipe(long_memory_op);
%}

instruct membar_acquire_lock() %{
  match(MemBarAcquire);
  predicate(Matcher::prior_fast_lock(n));
  ins_cost(0);

  size(0);
  format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
  ins_encode( );
  ins_pipe(empty);
%}

instruct membar_release() %{
  match(MemBarRelease);
  ins_cost(4*MEMORY_REF_COST);

  size(0);
  format %{ "MEMBAR-release" %}
  ins_encode( enc_membar_release );
  ins_pipe(long_memory_op);
%}

instruct membar_release_lock() %{
  match(MemBarRelease);
  predicate(Matcher::post_fast_unlock(n));
  ins_cost(0);

  size(0);
  format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
  ins_encode( );
  ins_pipe(empty);
%}

instruct membar_volatile() %{
  match(MemBarVolatile);
  ins_cost(4*MEMORY_REF_COST);

  size(4);
  format %{ "MEMBAR-volatile" %}
  ins_encode( enc_membar_volatile );
  ins_pipe(long_memory_op);
%}

instruct unnecessary_membar_volatile() %{
  match(MemBarVolatile);
  predicate(Matcher::post_store_load_barrier(n));
  ins_cost(0);

  size(0);
  format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
  ins_encode( );
  ins_pipe(empty);
%}

//----------Register Move Instructions-----------------------------------------
instruct roundDouble_nop(regD dst) %{
  match(Set dst (RoundDouble dst));
  ins_cost(0);
  // SPARC results are already "rounded" (i.e., normal-format IEEE)
  ins_encode( );
  ins_pipe(empty);
%}


instruct roundFloat_nop(regF dst) %{
  match(Set dst (RoundFloat dst));
  ins_cost(0);
  // SPARC results are already "rounded" (i.e., normal-format IEEE)
  ins_encode( );
  ins_pipe(empty);
%}


// Cast Index to Pointer for unsafe natives
instruct castX2P(iRegX src, iRegP dst) %{
  match(Set dst (CastX2P src));

  format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
  ins_encode( form3_g0_rs2_rd_move( src, dst ) );
  ins_pipe(ialu_reg);
%}

// Cast Pointer to Index for unsafe natives
instruct castP2X(iRegP src, iRegX dst) %{
  match(Set dst (CastP2X src));

  format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
  ins_encode( form3_g0_rs2_rd_move( src, dst ) );
  ins_pipe(ialu_reg);
%}

instruct stfSSD(stackSlotD stkSlot, regD src) %{
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
  match(Set stkSlot src);   // chain rule
  ins_cost(MEMORY_REF_COST);
  format %{ "STDF   $src,$stkSlot\t!stk" %}
  opcode(Assembler::stdf_op3);
6407
  ins_encode(simple_form3_mem_reg(stkSlot, src));
D
duke 已提交
6408 6409 6410 6411 6412 6413 6414 6415 6416
  ins_pipe(fstoreD_stk_reg);
%}

instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
  match(Set dst stkSlot);   // chain rule
  ins_cost(MEMORY_REF_COST);
  format %{ "LDDF   $stkSlot,$dst\t!stk" %}
  opcode(Assembler::lddf_op3);
6417
  ins_encode(simple_form3_mem_reg(stkSlot, dst));
D
duke 已提交
6418 6419 6420 6421 6422 6423 6424 6425 6426
  ins_pipe(floadD_stk);
%}

instruct stfSSF(stackSlotF stkSlot, regF src) %{
  // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
  match(Set stkSlot src);   // chain rule
  ins_cost(MEMORY_REF_COST);
  format %{ "STF   $src,$stkSlot\t!stk" %}
  opcode(Assembler::stf_op3);
6427
  ins_encode(simple_form3_mem_reg(stkSlot, src));
D
duke 已提交
6428 6429 6430 6431 6432 6433 6434 6435 6436 6437 6438 6439 6440 6441 6442 6443 6444 6445 6446 6447 6448 6449 6450 6451 6452 6453 6454 6455 6456 6457 6458 6459 6460 6461 6462 6463 6464 6465 6466
  ins_pipe(fstoreF_stk_reg);
%}

//----------Conditional Move---------------------------------------------------
// Conditional move
instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
  match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp $pcc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
  match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp $pcc,$src,$dst" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
  ins_cost(140);
  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_imm);
%}

6467
instruct cmovII_U_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
D
duke 已提交
6468 6469 6470 6471 6472 6473 6474 6475
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_reg);
%}

6476
instruct cmovII_U_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
D
duke 已提交
6477 6478 6479 6480 6481 6482 6483 6484 6485 6486 6487 6488 6489 6490 6491 6492 6493 6494 6495 6496 6497 6498 6499 6500 6501 6502
  match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
  ins_cost(140);
  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
  match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp $fcc,$src,$dst" %}
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_reg);
%}

instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
  match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
  ins_cost(140);
  size(4);
  format %{ "MOV$cmp $fcc,$src,$dst" %}
  ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_imm);
%}

6503 6504 6505 6506 6507 6508 6509 6510 6511 6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524 6525 6526 6527 6528 6529 6530
// Conditional move for RegN. Only cmov(reg,reg).
instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
  match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp $pcc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_reg);
%}

// This instruction also works with CmpN so we don't need cmovNN_reg.
instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
  match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
  match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp $fcc,$src,$dst" %}
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_reg);
%}

D
duke 已提交
6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542 6543 6544 6545 6546 6547
// Conditional move
instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
  match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
  match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_imm);
%}

6548
// This instruction also works with CmpN so we don't need cmovPN_reg.
D
duke 已提交
6549 6550 6551 6552 6553 6554 6555 6556 6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567 6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586 6587 6588 6589 6590 6591 6592 6593 6594 6595 6596 6597 6598 6599 6600 6601 6602 6603 6604 6605 6606 6607 6608 6609 6610 6611 6612 6613 6614 6615 6616 6617 6618 6619 6620 6621 6622 6623 6624 6625 6626 6627 6628 6629 6630 6631 6632 6633 6634 6635 6636 6637 6638 6639 6640 6641 6642 6643 6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654 6655 6656 6657 6658 6659 6660 6661 6662 6663 6664 6665 6666 6667 6668 6669 6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688 6689 6690 6691 6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711 6712 6713 6714 6715 6716 6717 6718 6719 6720 6721 6722 6723 6724 6725 6726 6727 6728 6729 6730 6731 6732 6733 6734 6735 6736 6737 6738 6739 6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768 6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795 6796 6797 6798 6799 6800 6801 6802 6803 6804 6805 6806 6807 6808 6809 6810 6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828
instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
  ins_cost(150);

  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
  match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
  ins_cost(140);

  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
  match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "MOV$cmp $fcc,$src,$dst" %}
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_imm);
%}

instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
  match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
  ins_cost(140);
  size(4);
  format %{ "MOV$cmp $fcc,$src,$dst" %}
  ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_imm);
%}

// Conditional move
instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
  match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  opcode(0x101);
  format %{ "FMOVD$cmp $pcc,$src,$dst" %}
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(int_conditional_float_move);
%}

instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
  match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
  ins_cost(150);

  size(4);
  format %{ "FMOVS$cmp $icc,$src,$dst" %}
  opcode(0x101);
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(int_conditional_float_move);
%}

// Conditional move,
instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
  match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "FMOVF$cmp $fcc,$src,$dst" %}
  opcode(0x1);
  ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
  ins_pipe(int_conditional_double_move);
%}

// Conditional move
instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
  match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  opcode(0x102);
  format %{ "FMOVD$cmp $pcc,$src,$dst" %}
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(int_conditional_double_move);
%}

instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
  match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
  ins_cost(150);

  size(4);
  format %{ "FMOVD$cmp $icc,$src,$dst" %}
  opcode(0x102);
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(int_conditional_double_move);
%}

// Conditional move,
instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
  match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);
  size(4);
  format %{ "FMOVD$cmp $fcc,$src,$dst" %}
  opcode(0x2);
  ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
  ins_pipe(int_conditional_double_move);
%}

// Conditional move
instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
  match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
  match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
  match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
  ins_cost(150);

  size(4);
  format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
  ins_pipe(ialu_reg);
%}


instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
  match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
  ins_cost(150);

  size(4);
  format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
  ins_pipe(ialu_reg);
%}



//----------OS and Locking Instructions----------------------------------------

// This name is KNOWN by the ADLC and cannot be changed.
// The ADLC forces a 'TypeRawPtr::BOTTOM' output type
// for this guy.
instruct tlsLoadP(g2RegP dst) %{
  match(Set dst (ThreadLocal));

  size(0);
  ins_cost(0);
  format %{ "# TLS is in G2" %}
  ins_encode( /*empty encoding*/ );
  ins_pipe(ialu_none);
%}

instruct checkCastPP( iRegP dst ) %{
  match(Set dst (CheckCastPP dst));

  size(0);
  format %{ "# checkcastPP of $dst" %}
  ins_encode( /*empty encoding*/ );
  ins_pipe(empty);
%}


instruct castPP( iRegP dst ) %{
  match(Set dst (CastPP dst));
  format %{ "# castPP of $dst" %}
  ins_encode( /*empty encoding*/ );
  ins_pipe(empty);
%}

instruct castII( iRegI dst ) %{
  match(Set dst (CastII dst));
  format %{ "# castII of $dst" %}
  ins_encode( /*empty encoding*/ );
  ins_cost(0);
  ins_pipe(empty);
%}

//----------Arithmetic Instructions--------------------------------------------
// Addition Instructions
// Register Addition
instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (AddI src1 src2));

  size(4);
  format %{ "ADD    $src1,$src2,$dst" %}
  ins_encode %{
    __ add($src1$$Register, $src2$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg_reg);
%}

// Immediate Addition
instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (AddI src1 src2));

  size(4);
  format %{ "ADD    $src1,$src2,$dst" %}
  opcode(Assembler::add_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Pointer Register Addition
instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
  match(Set dst (AddP src1 src2));

  size(4);
  format %{ "ADD    $src1,$src2,$dst" %}
  opcode(Assembler::add_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Pointer Immediate Addition
instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
  match(Set dst (AddP src1 src2));

  size(4);
  format %{ "ADD    $src1,$src2,$dst" %}
  opcode(Assembler::add_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Long Addition
instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (AddL src1 src2));

  size(4);
  format %{ "ADD    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::add_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
  match(Set dst (AddL src1 con));

  size(4);
  format %{ "ADD    $src1,$con,$dst" %}
  opcode(Assembler::add_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
  ins_pipe(ialu_reg_imm);
%}

//----------Conditional_store--------------------------------------------------
// Conditional-store of the updated heap-top.
// Used during allocation of the shared heap.
// Sets flags (EQ) on success.  Implemented with a CASA on Sparc.

// LoadP-locked.  Same as a regular pointer load when used with a compare-swap
instruct loadPLocked(iRegP dst, memory mem) %{
  match(Set dst (LoadPLocked mem));
  ins_cost(MEMORY_REF_COST);

#ifndef _LP64
  size(4);
  format %{ "LDUW   $mem,$dst\t! ptr" %}
  opcode(Assembler::lduw_op3, 0, REGP_OP);
#else
  format %{ "LDX    $mem,$dst\t! ptr" %}
  opcode(Assembler::ldx_op3, 0, REGP_OP);
#endif
  ins_encode( form3_mem_reg( mem, dst ) );
  ins_pipe(iload_mem);
%}

// LoadL-locked.  Same as a regular long load when used with a compare-swap
instruct loadLLocked(iRegL dst, memory mem) %{
  match(Set dst (LoadLLocked mem));
  ins_cost(MEMORY_REF_COST);
  size(4);
  format %{ "LDX    $mem,$dst\t! long" %}
  opcode(Assembler::ldx_op3);
6829
  ins_encode(simple_form3_mem_reg( mem, dst ) );
D
duke 已提交
6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841
  ins_pipe(iload_mem);
%}

instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
  match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
  effect( KILL newval );
  format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
            "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
  ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
  ins_pipe( long_memory_op );
%}

6842 6843 6844 6845 6846 6847 6848
// Conditional-store of an int value.
instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
  match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
  effect( KILL newval );
  format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
            "CMP    $oldval,$newval\t\t! See if we made progress"  %}
  ins_encode( enc_cas(mem_ptr,oldval,newval) );
D
duke 已提交
6849 6850 6851
  ins_pipe( long_memory_op );
%}

6852 6853 6854 6855 6856 6857 6858
// Conditional-store of a long value.
instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
  match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
  effect( KILL newval );
  format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
            "CMP    $oldval,$newval\t\t! See if we made progress"  %}
  ins_encode( enc_cas(mem_ptr,oldval,newval) );
D
duke 已提交
6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893 6894 6895 6896 6897 6898 6899
  ins_pipe( long_memory_op );
%}

// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them

instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
  match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
  format %{
            "MOV    $newval,O7\n\t"
            "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
            "MOV    1,$res\n\t"
            "MOVne  xcc,R_G0,$res"
  %}
  ins_encode( enc_casx(mem_ptr, oldval, newval),
              enc_lflags_ne_to_boolean(res) );
  ins_pipe( long_memory_op );
%}


instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
  match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
  format %{
            "MOV    $newval,O7\n\t"
            "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
            "MOV    1,$res\n\t"
            "MOVne  icc,R_G0,$res"
  %}
  ins_encode( enc_casi(mem_ptr, oldval, newval),
              enc_iflags_ne_to_boolean(res) );
  ins_pipe( long_memory_op );
%}

instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
  match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
  format %{
            "MOV    $newval,O7\n\t"
6900
            "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
D
duke 已提交
6901 6902 6903 6904
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
            "MOV    1,$res\n\t"
            "MOVne  xcc,R_G0,$res"
  %}
6905
#ifdef _LP64
D
duke 已提交
6906 6907 6908
  ins_encode( enc_casx(mem_ptr, oldval, newval),
              enc_lflags_ne_to_boolean(res) );
#else
6909 6910 6911 6912 6913 6914
  ins_encode( enc_casi(mem_ptr, oldval, newval),
              enc_iflags_ne_to_boolean(res) );
#endif
  ins_pipe( long_memory_op );
%}

6915
instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
6916
  match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
6917
  effect( USE mem_ptr, KILL ccr, KILL tmp1);
D
duke 已提交
6918 6919 6920 6921 6922 6923 6924
  format %{
            "MOV    $newval,O7\n\t"
            "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
            "CMP    $oldval,O7\t\t! See if we made progress\n\t"
            "MOV    1,$res\n\t"
            "MOVne  icc,R_G0,$res"
  %}
6925 6926
  ins_encode( enc_casi(mem_ptr, oldval, newval),
              enc_iflags_ne_to_boolean(res) );
D
duke 已提交
6927 6928 6929 6930 6931 6932 6933 6934 6935 6936 6937 6938 6939 6940 6941 6942 6943 6944 6945 6946 6947 6948 6949 6950 6951 6952 6953 6954 6955 6956 6957 6958 6959 6960 6961 6962 6963 6964 6965 6966 6967 6968 6969 6970 6971 6972 6973 6974 6975 6976 6977 6978 6979 6980 6981 6982 6983 6984 6985 6986 6987 6988 6989 6990 6991 6992 6993 6994 6995 6996 6997 6998 6999 7000 7001 7002 7003 7004 7005 7006 7007 7008 7009 7010 7011 7012 7013 7014 7015 7016 7017 7018 7019 7020 7021 7022 7023 7024 7025 7026 7027 7028 7029 7030 7031 7032 7033 7034 7035 7036 7037 7038 7039 7040 7041 7042 7043 7044 7045 7046 7047 7048 7049 7050 7051 7052 7053 7054 7055 7056 7057 7058 7059 7060 7061 7062 7063 7064 7065 7066 7067 7068 7069 7070 7071 7072 7073 7074 7075 7076
  ins_pipe( long_memory_op );
%}

//---------------------
// Subtraction Instructions
// Register Subtraction
instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (SubI src1 src2));

  size(4);
  format %{ "SUB    $src1,$src2,$dst" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Immediate Subtraction
instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (SubI src1 src2));

  size(4);
  format %{ "SUB    $src1,$src2,$dst" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
  match(Set dst (SubI zero src2));

  size(4);
  format %{ "NEG    $src2,$dst" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
  ins_pipe(ialu_zero_reg);
%}

// Long subtraction
instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (SubL src1 src2));

  size(4);
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Immediate Subtraction
instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
  match(Set dst (SubL src1 con));

  size(4);
  format %{ "SUB    $src1,$con,$dst\t! long" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Long negation
instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
  match(Set dst (SubL zero src2));

  size(4);
  format %{ "NEG    $src2,$dst\t! long" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
  ins_pipe(ialu_zero_reg);
%}

// Multiplication Instructions
// Integer Multiplication
// Register Multiplication
instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (MulI src1 src2));

  size(4);
  format %{ "MULX   $src1,$src2,$dst" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(imul_reg_reg);
%}

// Immediate Multiplication
instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (MulI src1 src2));

  size(4);
  format %{ "MULX   $src1,$src2,$dst" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(imul_reg_imm);
%}

instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (MulL src1 src2));
  ins_cost(DEFAULT_COST * 5);
  size(4);
  format %{ "MULX   $src1,$src2,$dst\t! long" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(mulL_reg_reg);
%}

// Immediate Multiplication
instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
  match(Set dst (MulL src1 src2));
  ins_cost(DEFAULT_COST * 5);
  size(4);
  format %{ "MULX   $src1,$src2,$dst" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(mulL_reg_imm);
%}

// Integer Division
// Register Division
instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
  match(Set dst (DivI src1 src2));
  ins_cost((2+71)*DEFAULT_COST);

  format %{ "SRA     $src2,0,$src2\n\t"
            "SRA     $src1,0,$src1\n\t"
            "SDIVX   $src1,$src2,$dst" %}
  ins_encode( idiv_reg( src1, src2, dst ) );
  ins_pipe(sdiv_reg_reg);
%}

// Immediate Division
instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
  match(Set dst (DivI src1 src2));
  ins_cost((2+71)*DEFAULT_COST);

  format %{ "SRA     $src1,0,$src1\n\t"
            "SDIVX   $src1,$src2,$dst" %}
  ins_encode( idiv_imm( src1, src2, dst ) );
  ins_pipe(sdiv_reg_imm);
%}

//----------Div-By-10-Expansion------------------------------------------------
// Extract hi bits of a 32x32->64 bit multiply.
// Expand rule only, not matched
instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
  effect( DEF dst, USE src1, USE src2 );
  format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
            "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
  ins_encode( enc_mul_hi(dst,src1,src2));
  ins_pipe(sdiv_reg_reg);
%}

T
twisti 已提交
7077
// Magic constant, reciprocal of 10
D
duke 已提交
7078 7079 7080 7081 7082 7083 7084 7085 7086
instruct loadConI_x66666667(iRegIsafe dst) %{
  effect( DEF dst );

  size(8);
  format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
  ins_encode( Set32(0x66666667, dst) );
  ins_pipe(ialu_hi_lo_reg);
%}

T
twisti 已提交
7087
// Register Shift Right Arithmetic Long by 32-63
D
duke 已提交
7088 7089 7090 7091 7092 7093 7094 7095 7096 7097 7098 7099 7100 7101 7102 7103 7104 7105 7106 7107 7108 7109 7110 7111 7112 7113 7114 7115 7116 7117 7118 7119 7120 7121 7122 7123 7124 7125 7126 7127 7128 7129 7130 7131 7132 7133 7134 7135 7136 7137 7138 7139 7140 7141 7142 7143 7144 7145 7146 7147 7148 7149 7150 7151 7152 7153 7154 7155 7156 7157 7158 7159 7160 7161 7162 7163 7164 7165 7166 7167 7168 7169 7170 7171 7172 7173 7174 7175 7176 7177 7178 7179 7180 7181 7182 7183 7184 7185 7186 7187 7188 7189 7190 7191 7192 7193 7194 7195 7196 7197 7198 7199 7200 7201 7202 7203 7204 7205 7206 7207 7208 7209 7210 7211 7212 7213 7214 7215 7216 7217 7218 7219 7220 7221 7222 7223 7224 7225 7226 7227 7228 7229 7230 7231 7232 7233 7234 7235 7236 7237 7238 7239 7240 7241 7242 7243 7244 7245 7246 7247 7248 7249 7250 7251 7252 7253 7254 7255 7256 7257 7258 7259 7260 7261 7262 7263 7264 7265 7266 7267 7268 7269 7270 7271 7272 7273 7274 7275 7276 7277 7278 7279 7280 7281 7282 7283 7284 7285 7286 7287 7288 7289 7290 7291 7292 7293 7294 7295 7296 7297 7298 7299 7300 7301 7302 7303 7304 7305 7306 7307 7308 7309 7310 7311 7312 7313 7314 7315 7316 7317 7318 7319 7320 7321 7322 7323 7324 7325 7326 7327 7328 7329 7330 7331 7332 7333 7334 7335 7336 7337 7338 7339 7340 7341 7342 7343 7344 7345 7346 7347 7348 7349 7350 7351 7352 7353 7354 7355 7356 7357 7358 7359 7360 7361 7362 7363 7364 7365 7366 7367 7368 7369 7370 7371 7372 7373 7374 7375 7376 7377 7378 7379 7380 7381 7382 7383 7384 7385 7386 7387 7388 7389 7390 7391 7392 7393 7394 7395 7396 7397 7398 7399 7400 7401 7402 7403 7404 7405 7406 7407 7408 7409 7410 7411 7412 7413 7414 7415 7416 7417 7418 7419 7420 7421 7422 7423 7424 7425 7426 7427 7428 7429 7430 7431 7432 7433 7434 7435 7436 7437 7438 7439 7440 7441 7442 7443 7444 7445 7446 7447 7448 7449 7450 7451 7452 7453 7454 7455 7456 7457 7458 7459 7460 7461 7462 7463 7464 7465 7466 7467 7468 7469 7470 7471 7472 7473 7474 7475 7476 7477 7478 7479 7480 7481 7482 7483 7484 7485 7486 7487 7488 7489 7490 7491 7492 7493 7494 7495 7496 7497 7498 7499 7500 7501 7502 7503 7504 7505 7506 7507 7508 7509 7510 7511 7512 7513 7514 7515 7516 7517 7518 7519 7520 7521 7522 7523 7524 7525 7526 7527 7528 7529 7530 7531 7532 7533 7534 7535 7536 7537 7538 7539 7540 7541 7542 7543 7544 7545 7546 7547 7548 7549 7550 7551 7552 7553 7554 7555 7556 7557 7558 7559 7560 7561 7562 7563 7564 7565 7566 7567 7568 7569 7570 7571 7572 7573 7574 7575 7576 7577 7578 7579 7580 7581 7582 7583 7584 7585 7586 7587 7588 7589 7590 7591 7592 7593 7594 7595 7596 7597 7598 7599 7600 7601 7602 7603 7604 7605 7606 7607 7608 7609 7610 7611 7612 7613 7614 7615 7616 7617 7618 7619 7620 7621 7622 7623 7624 7625 7626 7627 7628 7629 7630 7631 7632 7633 7634 7635 7636 7637 7638 7639 7640
instruct sra_31( iRegI dst, iRegI src ) %{
  effect( DEF dst, USE src );
  format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
  ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
  ins_pipe(ialu_reg_reg);
%}

// Arithmetic Shift Right by 8-bit immediate
instruct sra_reg_2( iRegI dst, iRegI src ) %{
  effect( DEF dst, USE src );
  format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
  opcode(Assembler::sra_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Integer DIV with 10
instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
  match(Set dst (DivI src div));
  ins_cost((6+6)*DEFAULT_COST);
  expand %{
    iRegIsafe tmp1;               // Killed temps;
    iRegIsafe tmp2;               // Killed temps;
    iRegI tmp3;                   // Killed temps;
    iRegI tmp4;                   // Killed temps;
    loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
    mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
    sra_31( tmp3, src );          // SRA  src,31 -> tmp3
    sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
    subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
  %}
%}

// Register Long Division
instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (DivL src1 src2));
  ins_cost(DEFAULT_COST*71);
  size(4);
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(divL_reg_reg);
%}

// Register Long Division
instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
  match(Set dst (DivL src1 src2));
  ins_cost(DEFAULT_COST*71);
  size(4);
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(divL_reg_imm);
%}

// Integer Remainder
// Register Remainder
instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
  match(Set dst (ModI src1 src2));
  effect( KILL ccr, KILL temp);

  format %{ "SREM   $src1,$src2,$dst" %}
  ins_encode( irem_reg(src1, src2, dst, temp) );
  ins_pipe(sdiv_reg_reg);
%}

// Immediate Remainder
instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
  match(Set dst (ModI src1 src2));
  effect( KILL ccr, KILL temp);

  format %{ "SREM   $src1,$src2,$dst" %}
  ins_encode( irem_imm(src1, src2, dst, temp) );
  ins_pipe(sdiv_reg_imm);
%}

// Register Long Remainder
instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(divL_reg_reg);
%}

// Register Long Division
instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sdivx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(divL_reg_imm);
%}

instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "MULX   $src1,$src2,$dst\t! long" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(mulL_reg_reg);
%}

// Immediate Multiplication
instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "MULX   $src1,$src2,$dst" %}
  opcode(Assembler::mulx_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(mulL_reg_imm);
%}

instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "SUB    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::sub_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Long Remainder
instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (ModL src1 src2));
  ins_cost(DEFAULT_COST*(71 + 6 + 1));
  expand %{
    iRegL tmp1;
    iRegL tmp2;
    divL_reg_reg_1(tmp1, src1, src2);
    mulL_reg_reg_1(tmp2, tmp1, src2);
    subL_reg_reg_1(dst,  src1, tmp2);
  %}
%}

// Register Long Remainder
instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
  match(Set dst (ModL src1 src2));
  ins_cost(DEFAULT_COST*(71 + 6 + 1));
  expand %{
    iRegL tmp1;
    iRegL tmp2;
    divL_reg_imm13_1(tmp1, src1, src2);
    mulL_reg_imm13_1(tmp2, tmp1, src2);
    subL_reg_reg_2  (dst,  src1, tmp2);
  %}
%}

// Integer Shift Instructions
// Register Shift Left
instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (LShiftI src1 src2));

  size(4);
  format %{ "SLL    $src1,$src2,$dst" %}
  opcode(Assembler::sll_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Shift Left Immediate
instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
  match(Set dst (LShiftI src1 src2));

  size(4);
  format %{ "SLL    $src1,$src2,$dst" %}
  opcode(Assembler::sll_op3, Assembler::arith_op);
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Shift Left
instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
  match(Set dst (LShiftL src1 src2));

  size(4);
  format %{ "SLLX   $src1,$src2,$dst" %}
  opcode(Assembler::sllx_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Shift Left Immediate
instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
  match(Set dst (LShiftL src1 src2));

  size(4);
  format %{ "SLLX   $src1,$src2,$dst" %}
  opcode(Assembler::sllx_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Arithmetic Shift Right
instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (RShiftI src1 src2));
  size(4);
  format %{ "SRA    $src1,$src2,$dst" %}
  opcode(Assembler::sra_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Arithmetic Shift Right Immediate
instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
  match(Set dst (RShiftI src1 src2));

  size(4);
  format %{ "SRA    $src1,$src2,$dst" %}
  opcode(Assembler::sra_op3, Assembler::arith_op);
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Shift Right Arithmatic Long
instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
  match(Set dst (RShiftL src1 src2));

  size(4);
  format %{ "SRAX   $src1,$src2,$dst" %}
  opcode(Assembler::srax_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Shift Left Immediate
instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
  match(Set dst (RShiftL src1 src2));

  size(4);
  format %{ "SRAX   $src1,$src2,$dst" %}
  opcode(Assembler::srax_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Shift Right
instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (URShiftI src1 src2));

  size(4);
  format %{ "SRL    $src1,$src2,$dst" %}
  opcode(Assembler::srl_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Shift Right Immediate
instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
  match(Set dst (URShiftI src1 src2));

  size(4);
  format %{ "SRL    $src1,$src2,$dst" %}
  opcode(Assembler::srl_op3, Assembler::arith_op);
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Shift Right
instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
  match(Set dst (URShiftL src1 src2));

  size(4);
  format %{ "SRLX   $src1,$src2,$dst" %}
  opcode(Assembler::srlx_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Register Shift Right Immediate
instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
  match(Set dst (URShiftL src1 src2));

  size(4);
  format %{ "SRLX   $src1,$src2,$dst" %}
  opcode(Assembler::srlx_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Shift Right Immediate with a CastP2X
#ifdef _LP64
instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
  match(Set dst (URShiftL (CastP2X src1) src2));
  size(4);
  format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
  opcode(Assembler::srlx_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}
#else
instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
  match(Set dst (URShiftI (CastP2X src1) src2));
  size(4);
  format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
  opcode(Assembler::srl_op3, Assembler::arith_op);
  ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}
#endif


//----------Floating Point Arithmetic Instructions-----------------------------

//  Add float single precision
instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
  match(Set dst (AddF src1 src2));

  size(4);
  format %{ "FADDS  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
  ins_pipe(faddF_reg_reg);
%}

//  Add float double precision
instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
  match(Set dst (AddD src1 src2));

  size(4);
  format %{ "FADDD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(faddD_reg_reg);
%}

//  Sub float single precision
instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
  match(Set dst (SubF src1 src2));

  size(4);
  format %{ "FSUBS  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
  ins_pipe(faddF_reg_reg);
%}

//  Sub float double precision
instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
  match(Set dst (SubD src1 src2));

  size(4);
  format %{ "FSUBD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(faddD_reg_reg);
%}

//  Mul float single precision
instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
  match(Set dst (MulF src1 src2));

  size(4);
  format %{ "FMULS  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
  ins_pipe(fmulF_reg_reg);
%}

//  Mul float double precision
instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
  match(Set dst (MulD src1 src2));

  size(4);
  format %{ "FMULD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(fmulD_reg_reg);
%}

//  Div float single precision
instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
  match(Set dst (DivF src1 src2));

  size(4);
  format %{ "FDIVS  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
  ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
  ins_pipe(fdivF_reg_reg);
%}

//  Div float double precision
instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
  match(Set dst (DivD src1 src2));

  size(4);
  format %{ "FDIVD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(fdivD_reg_reg);
%}

//  Absolute float double precision
instruct absD_reg(regD dst, regD src) %{
  match(Set dst (AbsD src));

  format %{ "FABSd  $src,$dst" %}
  ins_encode(fabsd(dst, src));
  ins_pipe(faddD_reg);
%}

//  Absolute float single precision
instruct absF_reg(regF dst, regF src) %{
  match(Set dst (AbsF src));

  format %{ "FABSs  $src,$dst" %}
  ins_encode(fabss(dst, src));
  ins_pipe(faddF_reg);
%}

instruct negF_reg(regF dst, regF src) %{
  match(Set dst (NegF src));

  size(4);
  format %{ "FNEGs  $src,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
  ins_encode(form3_opf_rs2F_rdF(src, dst));
  ins_pipe(faddF_reg);
%}

instruct negD_reg(regD dst, regD src) %{
  match(Set dst (NegD src));

  format %{ "FNEGd  $src,$dst" %}
  ins_encode(fnegd(dst, src));
  ins_pipe(faddD_reg);
%}

//  Sqrt float double precision
instruct sqrtF_reg_reg(regF dst, regF src) %{
  match(Set dst (ConvD2F (SqrtD (ConvF2D src))));

  size(4);
  format %{ "FSQRTS $src,$dst" %}
  ins_encode(fsqrts(dst, src));
  ins_pipe(fdivF_reg_reg);
%}

//  Sqrt float double precision
instruct sqrtD_reg_reg(regD dst, regD src) %{
  match(Set dst (SqrtD src));

  size(4);
  format %{ "FSQRTD $src,$dst" %}
  ins_encode(fsqrtd(dst, src));
  ins_pipe(fdivD_reg_reg);
%}

//----------Logical Instructions-----------------------------------------------
// And Instructions
// Register And
instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (AndI src1 src2));

  size(4);
  format %{ "AND    $src1,$src2,$dst" %}
  opcode(Assembler::and_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Immediate And
instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (AndI src1 src2));

  size(4);
  format %{ "AND    $src1,$src2,$dst" %}
  opcode(Assembler::and_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register And Long
instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (AndL src1 src2));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "AND    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::and_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
  match(Set dst (AndL src1 con));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "AND    $src1,$con,$dst\t! long" %}
  opcode(Assembler::and_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Or Instructions
// Register Or
instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (OrI src1 src2));

  size(4);
  format %{ "OR     $src1,$src2,$dst" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Immediate Or
instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (OrI src1 src2));

  size(4);
  format %{ "OR     $src1,$src2,$dst" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Or Long
instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (OrL src1 src2));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "OR     $src1,$src2,$dst\t! long" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
  match(Set dst (OrL src1 con));
  ins_cost(DEFAULT_COST*2);

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "OR     $src1,$con,$dst\t! long" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
  ins_pipe(ialu_reg_imm);
%}

7641 7642 7643 7644 7645 7646 7647 7648 7649 7650 7651 7652 7653 7654 7655 7656 7657 7658 7659 7660 7661 7662 7663 7664 7665 7666 7667 7668
#ifndef _LP64

// Use sp_ptr_RegP to match G2 (TLS register) without spilling.
instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
  match(Set dst (OrI src1 (CastP2X src2)));

  size(4);
  format %{ "OR     $src1,$src2,$dst" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

#else

instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
  match(Set dst (OrL src1 (CastP2X src2)));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "OR     $src1,$src2,$dst\t! long" %}
  opcode(Assembler::or_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

#endif

D
duke 已提交
7669 7670 7671 7672 7673 7674 7675 7676 7677 7678 7679 7680 7681 7682 7683 7684 7685 7686 7687 7688 7689 7690 7691 7692 7693 7694 7695 7696 7697 7698 7699 7700 7701 7702 7703 7704 7705 7706 7707 7708 7709 7710 7711 7712 7713 7714 7715 7716 7717 7718 7719 7720 7721 7722 7723 7724 7725 7726 7727 7728 7729 7730 7731 7732 7733 7734 7735 7736 7737 7738 7739 7740 7741 7742 7743 7744 7745 7746 7747 7748 7749 7750 7751 7752 7753 7754 7755 7756 7757 7758 7759 7760 7761 7762 7763 7764 7765 7766 7767 7768 7769 7770 7771 7772 7773 7774 7775 7776 7777 7778 7779 7780 7781 7782 7783 7784 7785 7786 7787 7788 7789 7790 7791 7792 7793 7794 7795 7796 7797 7798 7799 7800 7801 7802 7803 7804 7805 7806 7807 7808 7809 7810 7811 7812 7813 7814 7815 7816 7817 7818 7819 7820 7821 7822 7823 7824 7825 7826 7827 7828 7829 7830 7831 7832 7833 7834 7835 7836 7837 7838 7839 7840 7841 7842 7843 7844 7845 7846 7847 7848 7849 7850 7851 7852 7853 7854 7855 7856 7857 7858 7859 7860 7861 7862 7863 7864 7865 7866 7867 7868 7869 7870 7871 7872 7873 7874 7875 7876 7877 7878 7879 7880 7881 7882 7883 7884 7885 7886 7887 7888 7889 7890 7891 7892 7893 7894 7895 7896 7897 7898 7899 7900 7901 7902 7903 7904 7905 7906 7907 7908 7909 7910 7911 7912 7913 7914 7915 7916 7917 7918 7919 7920 7921 7922 7923 7924 7925 7926 7927 7928 7929
// Xor Instructions
// Register Xor
instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
  match(Set dst (XorI src1 src2));

  size(4);
  format %{ "XOR    $src1,$src2,$dst" %}
  opcode(Assembler::xor_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Immediate Xor
instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
  match(Set dst (XorI src1 src2));

  size(4);
  format %{ "XOR    $src1,$src2,$dst" %}
  opcode(Assembler::xor_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Register Xor Long
instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
  match(Set dst (XorL src1 src2));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "XOR    $src1,$src2,$dst\t! long" %}
  opcode(Assembler::xor_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
  match(Set dst (XorL src1 con));

  ins_cost(DEFAULT_COST);
  size(4);
  format %{ "XOR    $src1,$con,$dst\t! long" %}
  opcode(Assembler::xor_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
  ins_pipe(ialu_reg_imm);
%}

//----------Convert to Boolean-------------------------------------------------
// Nice hack for 32-bit tests but doesn't work for
// 64-bit pointers.
instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
  match(Set dst (Conv2B src));
  effect( KILL ccr );
  ins_cost(DEFAULT_COST*2);
  format %{ "CMP    R_G0,$src\n\t"
            "ADDX   R_G0,0,$dst" %}
  ins_encode( enc_to_bool( src, dst ) );
  ins_pipe(ialu_reg_ialu);
%}

#ifndef _LP64
instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
  match(Set dst (Conv2B src));
  effect( KILL ccr );
  ins_cost(DEFAULT_COST*2);
  format %{ "CMP    R_G0,$src\n\t"
            "ADDX   R_G0,0,$dst" %}
  ins_encode( enc_to_bool( src, dst ) );
  ins_pipe(ialu_reg_ialu);
%}
#else
instruct convP2B( iRegI dst, iRegP src ) %{
  match(Set dst (Conv2B src));
  ins_cost(DEFAULT_COST*2);
  format %{ "MOV    $src,$dst\n\t"
            "MOVRNZ $src,1,$dst" %}
  ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
  ins_pipe(ialu_clr_and_mover);
%}
#endif

instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
  match(Set dst (CmpLTMask p q));
  effect( KILL ccr );
  ins_cost(DEFAULT_COST*4);
  format %{ "CMP    $p,$q\n\t"
            "MOV    #0,$dst\n\t"
            "BLT,a  .+8\n\t"
            "MOV    #-1,$dst" %}
  ins_encode( enc_ltmask(p,q,dst) );
  ins_pipe(ialu_reg_reg_ialu);
%}

instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
  match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
  effect(KILL ccr, TEMP tmp);
  ins_cost(DEFAULT_COST*3);

  format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
            "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
            "MOVl   $tmp,$p\t! p' < 0 ? p'+y : p'" %}
  ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
  ins_pipe( cadd_cmpltmask );
%}

instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
  match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y)));
  effect( KILL ccr, TEMP tmp);
  ins_cost(DEFAULT_COST*3);

  format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
            "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
            "MOVl   $tmp,$p\t! p' < 0 ? p'+y : p'" %}
  ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) );
  ins_pipe( cadd_cmpltmask );
%}

//----------Arithmetic Conversion Instructions---------------------------------
// The conversions operations are all Alpha sorted.  Please keep it that way!

instruct convD2F_reg(regF dst, regD src) %{
  match(Set dst (ConvD2F src));
  size(4);
  format %{ "FDTOS  $src,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
  ins_encode(form3_opf_rs2D_rdF(src, dst));
  ins_pipe(fcvtD2F);
%}


// Convert a double to an int in a float register.
// If the double is a NAN, stuff a zero in instead.
instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
  effect(DEF dst, USE src, KILL fcc0);
  format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
            "FDTOI  $src,$dst\t! convert in delay slot\n\t"
            "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
            "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
      "skip:" %}
  ins_encode(form_d2i_helper(src,dst));
  ins_pipe(fcvtD2I);
%}

instruct convD2I_reg(stackSlotI dst, regD src) %{
  match(Set dst (ConvD2I src));
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
  expand %{
    regF tmp;
    convD2I_helper(tmp, src);
    regF_to_stkI(dst, tmp);
  %}
%}

// Convert a double to a long in a double register.
// If the double is a NAN, stuff a zero in instead.
instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
  effect(DEF dst, USE src, KILL fcc0);
  format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
            "FDTOX  $src,$dst\t! convert in delay slot\n\t"
            "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
            "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
      "skip:" %}
  ins_encode(form_d2l_helper(src,dst));
  ins_pipe(fcvtD2L);
%}


// Double to Long conversion
instruct convD2L_reg(stackSlotL dst, regD src) %{
  match(Set dst (ConvD2L src));
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
  expand %{
    regD tmp;
    convD2L_helper(tmp, src);
    regD_to_stkL(dst, tmp);
  %}
%}


instruct convF2D_reg(regD dst, regF src) %{
  match(Set dst (ConvF2D src));
  format %{ "FSTOD  $src,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
  ins_encode(form3_opf_rs2F_rdD(src, dst));
  ins_pipe(fcvtF2D);
%}


instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
  effect(DEF dst, USE src, KILL fcc0);
  format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
            "FSTOI  $src,$dst\t! convert in delay slot\n\t"
            "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
            "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
      "skip:" %}
  ins_encode(form_f2i_helper(src,dst));
  ins_pipe(fcvtF2I);
%}

instruct convF2I_reg(stackSlotI dst, regF src) %{
  match(Set dst (ConvF2I src));
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
  expand %{
    regF tmp;
    convF2I_helper(tmp, src);
    regF_to_stkI(dst, tmp);
  %}
%}


instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
  effect(DEF dst, USE src, KILL fcc0);
  format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
            "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
            "FSTOX  $src,$dst\t! convert in delay slot\n\t"
            "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
            "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
      "skip:" %}
  ins_encode(form_f2l_helper(src,dst));
  ins_pipe(fcvtF2L);
%}

// Float to Long conversion
instruct convF2L_reg(stackSlotL dst, regF src) %{
  match(Set dst (ConvF2L src));
  ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
  expand %{
    regD tmp;
    convF2L_helper(tmp, src);
    regD_to_stkL(dst, tmp);
  %}
%}


instruct convI2D_helper(regD dst, regF tmp) %{
  effect(USE tmp, DEF dst);
  format %{ "FITOD  $tmp,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
  ins_encode(form3_opf_rs2F_rdD(tmp, dst));
  ins_pipe(fcvtI2D);
%}

instruct convI2D_reg(stackSlotI src, regD dst) %{
  match(Set dst (ConvI2D src));
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  expand %{
    regF tmp;
    stkI_to_regF( tmp, src);
    convI2D_helper( dst, tmp);
  %}
%}

instruct convI2D_mem( regD_low dst, memory mem ) %{
  match(Set dst (ConvI2D (LoadI mem)));
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDF    $mem,$dst\n\t"
            "FITOD  $dst,$dst" %}
  opcode(Assembler::ldf_op3, Assembler::fitod_opf);
7930
  ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
D
duke 已提交
7931 7932 7933 7934 7935 7936 7937 7938 7939 7940 7941 7942 7943 7944 7945 7946 7947 7948 7949 7950 7951 7952 7953 7954 7955 7956 7957 7958 7959
  ins_pipe(floadF_mem);
%}


instruct convI2F_helper(regF dst, regF tmp) %{
  effect(DEF dst, USE tmp);
  format %{ "FITOS  $tmp,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
  ins_encode(form3_opf_rs2F_rdF(tmp, dst));
  ins_pipe(fcvtI2F);
%}

instruct convI2F_reg( regF dst, stackSlotI src ) %{
  match(Set dst (ConvI2F src));
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  expand %{
    regF tmp;
    stkI_to_regF(tmp,src);
    convI2F_helper(dst, tmp);
  %}
%}

instruct convI2F_mem( regF dst, memory mem ) %{
  match(Set dst (ConvI2F (LoadI mem)));
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDF    $mem,$dst\n\t"
            "FITOS  $dst,$dst" %}
  opcode(Assembler::ldf_op3, Assembler::fitos_opf);
7960
  ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
D
duke 已提交
7961 7962 7963 7964 7965 7966 7967 7968 7969 7970 7971 7972 7973 7974 7975 7976 7977 7978 7979 7980 7981 7982 7983 7984 7985 7986 7987 7988 7989 7990 7991 7992 7993 7994 7995 7996 7997 7998 7999 8000 8001
  ins_pipe(floadF_mem);
%}


instruct convI2L_reg(iRegL dst, iRegI src) %{
  match(Set dst (ConvI2L src));
  size(4);
  format %{ "SRA    $src,0,$dst\t! int->long" %}
  opcode(Assembler::sra_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Zero-extend convert int to long
instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
  match(Set dst (AndL (ConvI2L src) mask) );
  size(4);
  format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
  opcode(Assembler::srl_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
  ins_pipe(ialu_reg_reg);
%}

// Zero-extend long
instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
  match(Set dst (AndL src mask) );
  size(4);
  format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
  opcode(Assembler::srl_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
  ins_pipe(ialu_reg_reg);
%}

instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
  match(Set dst (MoveF2I src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDUW   $src,$dst\t! MoveF2I" %}
  opcode(Assembler::lduw_op3);
8002
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
8003 8004 8005 8006 8007 8008 8009 8010 8011 8012 8013
  ins_pipe(iload_mem);
%}

instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
  match(Set dst (MoveI2F src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDF    $src,$dst\t! MoveI2F" %}
  opcode(Assembler::ldf_op3);
8014
  ins_encode(simple_form3_mem_reg(src, dst));
D
duke 已提交
8015 8016 8017 8018 8019 8020 8021 8022 8023 8024 8025
  ins_pipe(floadF_stk);
%}

instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
  match(Set dst (MoveD2L src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDX    $src,$dst\t! MoveD2L" %}
  opcode(Assembler::ldx_op3);
8026
  ins_encode(simple_form3_mem_reg( src, dst ) );
D
duke 已提交
8027 8028 8029 8030 8031 8032 8033 8034 8035 8036 8037
  ins_pipe(iload_mem);
%}

instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
  match(Set dst (MoveL2D src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "LDDF   $src,$dst\t! MoveL2D" %}
  opcode(Assembler::lddf_op3);
8038
  ins_encode(simple_form3_mem_reg(src, dst));
D
duke 已提交
8039 8040 8041 8042 8043 8044 8045 8046 8047 8048 8049
  ins_pipe(floadD_stk);
%}

instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
  match(Set dst (MoveF2I src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STF   $src,$dst\t!MoveF2I" %}
  opcode(Assembler::stf_op3);
8050
  ins_encode(simple_form3_mem_reg(dst, src));
D
duke 已提交
8051 8052 8053 8054 8055 8056 8057 8058 8059 8060 8061
  ins_pipe(fstoreF_stk_reg);
%}

instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
  match(Set dst (MoveI2F src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STW    $src,$dst\t!MoveI2F" %}
  opcode(Assembler::stw_op3);
8062
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
8063 8064 8065 8066 8067 8068 8069 8070 8071 8072 8073
  ins_pipe(istore_mem_reg);
%}

instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
  match(Set dst (MoveD2L src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STDF   $src,$dst\t!MoveD2L" %}
  opcode(Assembler::stdf_op3);
8074
  ins_encode(simple_form3_mem_reg(dst, src));
D
duke 已提交
8075 8076 8077 8078 8079 8080 8081 8082 8083 8084 8085
  ins_pipe(fstoreD_stk_reg);
%}

instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
  match(Set dst (MoveL2D src));
  effect(DEF dst, USE src);
  ins_cost(MEMORY_REF_COST);

  size(4);
  format %{ "STX    $src,$dst\t!MoveL2D" %}
  opcode(Assembler::stx_op3);
8086
  ins_encode(simple_form3_mem_reg( dst, src ) );
D
duke 已提交
8087 8088 8089 8090 8091 8092 8093 8094 8095 8096 8097 8098 8099 8100 8101 8102 8103 8104 8105 8106 8107 8108 8109 8110 8111 8112 8113 8114 8115 8116 8117 8118 8119 8120 8121 8122 8123 8124 8125 8126 8127 8128 8129 8130 8131 8132 8133 8134 8135 8136 8137 8138 8139 8140 8141 8142 8143 8144 8145 8146 8147 8148 8149 8150 8151 8152 8153 8154 8155 8156 8157 8158 8159 8160 8161 8162 8163 8164 8165 8166 8167 8168 8169 8170 8171 8172 8173 8174 8175 8176 8177 8178 8179 8180 8181 8182 8183 8184 8185 8186 8187 8188 8189 8190 8191 8192 8193 8194 8195 8196 8197 8198 8199 8200 8201 8202 8203 8204 8205 8206 8207 8208 8209 8210 8211 8212 8213 8214 8215 8216 8217 8218 8219 8220 8221 8222 8223 8224 8225 8226 8227 8228 8229 8230 8231 8232 8233 8234 8235 8236 8237 8238 8239 8240 8241 8242 8243 8244 8245 8246 8247 8248 8249 8250 8251 8252 8253 8254 8255 8256 8257 8258 8259 8260 8261 8262 8263 8264 8265 8266 8267 8268 8269 8270 8271 8272 8273 8274 8275 8276 8277 8278 8279 8280 8281 8282 8283 8284 8285 8286 8287 8288 8289 8290 8291 8292 8293 8294 8295 8296 8297 8298 8299 8300 8301 8302 8303 8304 8305 8306 8307 8308 8309 8310 8311 8312 8313 8314 8315 8316 8317 8318 8319 8320 8321 8322 8323 8324 8325 8326 8327 8328 8329 8330 8331 8332 8333 8334 8335 8336 8337 8338 8339 8340 8341 8342 8343 8344 8345 8346 8347 8348 8349 8350 8351 8352 8353 8354 8355 8356 8357 8358 8359 8360 8361 8362 8363 8364 8365 8366 8367 8368 8369 8370 8371 8372 8373 8374 8375 8376 8377 8378 8379 8380 8381 8382 8383 8384 8385 8386 8387 8388 8389 8390 8391 8392 8393 8394 8395 8396 8397 8398 8399 8400 8401 8402 8403 8404 8405 8406 8407 8408 8409 8410 8411 8412 8413 8414 8415 8416 8417 8418 8419 8420 8421 8422 8423 8424 8425 8426 8427 8428 8429 8430 8431 8432 8433 8434 8435 8436 8437 8438 8439 8440 8441 8442 8443 8444 8445 8446 8447 8448 8449 8450 8451 8452 8453 8454 8455 8456 8457 8458 8459 8460 8461 8462 8463 8464 8465 8466 8467 8468 8469 8470 8471 8472 8473 8474 8475 8476 8477 8478 8479 8480 8481 8482 8483 8484 8485 8486 8487 8488 8489 8490 8491 8492 8493 8494 8495 8496 8497 8498 8499 8500 8501 8502 8503 8504 8505 8506 8507 8508 8509 8510 8511 8512 8513 8514 8515 8516 8517 8518 8519 8520 8521 8522 8523 8524 8525 8526 8527 8528 8529 8530 8531 8532 8533 8534 8535 8536 8537 8538 8539 8540 8541 8542 8543 8544 8545 8546
  ins_pipe(istore_mem_reg);
%}


//-----------
// Long to Double conversion using V8 opcodes.
// Still useful because cheetah traps and becomes
// amazingly slow for some common numbers.

// Magic constant, 0x43300000
instruct loadConI_x43300000(iRegI dst) %{
  effect(DEF dst);
  size(4);
  format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
  ins_encode(SetHi22(0x43300000, dst));
  ins_pipe(ialu_none);
%}

// Magic constant, 0x41f00000
instruct loadConI_x41f00000(iRegI dst) %{
  effect(DEF dst);
  size(4);
  format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
  ins_encode(SetHi22(0x41f00000, dst));
  ins_pipe(ialu_none);
%}

// Construct a double from two float halves
instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(8);
  format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
            "FMOVS  $src2.lo,$dst.lo" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
  ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
  ins_pipe(faddD_reg_reg);
%}

// Convert integer in high half of a double register (in the lower half of
// the double register file) to double
instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
  effect(DEF dst, USE src);
  size(4);
  format %{ "FITOD  $src,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
  ins_encode(form3_opf_rs2D_rdD(src, dst));
  ins_pipe(fcvtLHi2D);
%}

// Add float double precision
instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "FADDD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(faddD_reg_reg);
%}

// Sub float double precision
instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "FSUBD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(faddD_reg_reg);
%}

// Mul float double precision
instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
  effect(DEF dst, USE src1, USE src2);
  size(4);
  format %{ "FMULD  $src1,$src2,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
  ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
  ins_pipe(fmulD_reg_reg);
%}

instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
  match(Set dst (ConvL2D src));
  ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);

  expand %{
    regD_low   tmpsrc;
    iRegI      ix43300000;
    iRegI      ix41f00000;
    stackSlotL lx43300000;
    stackSlotL lx41f00000;
    regD_low   dx43300000;
    regD       dx41f00000;
    regD       tmp1;
    regD_low   tmp2;
    regD       tmp3;
    regD       tmp4;

    stkL_to_regD(tmpsrc, src);

    loadConI_x43300000(ix43300000);
    loadConI_x41f00000(ix41f00000);
    regI_to_stkLHi(lx43300000, ix43300000);
    regI_to_stkLHi(lx41f00000, ix41f00000);
    stkL_to_regD(dx43300000, lx43300000);
    stkL_to_regD(dx41f00000, lx41f00000);

    convI2D_regDHi_regD(tmp1, tmpsrc);
    regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
    subD_regD_regD(tmp3, tmp2, dx43300000);
    mulD_regD_regD(tmp4, tmp1, dx41f00000);
    addD_regD_regD(dst, tmp3, tmp4);
  %}
%}

// Long to Double conversion using fast fxtof
instruct convL2D_helper(regD dst, regD tmp) %{
  effect(DEF dst, USE tmp);
  size(4);
  format %{ "FXTOD  $tmp,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
  ins_encode(form3_opf_rs2D_rdD(tmp, dst));
  ins_pipe(fcvtL2D);
%}

instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{
  predicate(VM_Version::has_fast_fxtof());
  match(Set dst (ConvL2D src));
  ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
  expand %{
    regD tmp;
    stkL_to_regD(tmp, src);
    convL2D_helper(dst, tmp);
  %}
%}

//-----------
// Long to Float conversion using V8 opcodes.
// Still useful because cheetah traps and becomes
// amazingly slow for some common numbers.

// Long to Float conversion using fast fxtof
instruct convL2F_helper(regF dst, regD tmp) %{
  effect(DEF dst, USE tmp);
  size(4);
  format %{ "FXTOS  $tmp,$dst" %}
  opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
  ins_encode(form3_opf_rs2D_rdF(tmp, dst));
  ins_pipe(fcvtL2F);
%}

instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{
  match(Set dst (ConvL2F src));
  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  expand %{
    regD tmp;
    stkL_to_regD(tmp, src);
    convL2F_helper(dst, tmp);
  %}
%}
//-----------

instruct convL2I_reg(iRegI dst, iRegL src) %{
  match(Set dst (ConvL2I src));
#ifndef _LP64
  format %{ "MOV    $src.lo,$dst\t! long->int" %}
  ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
  ins_pipe(ialu_move_reg_I_to_L);
#else
  size(4);
  format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
  ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
  ins_pipe(ialu_reg);
#endif
%}

// Register Shift Right Immediate
instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
  match(Set dst (ConvL2I (RShiftL src cnt)));

  size(4);
  format %{ "SRAX   $src,$cnt,$dst" %}
  opcode(Assembler::srax_op3, Assembler::arith_op);
  ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
  ins_pipe(ialu_reg_imm);
%}

// Replicate scalar to packed byte values in Double register
instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{
  effect(DEF dst, USE src);
  format %{ "SLLX  $src,56,$dst\n\t"
            "SRLX  $dst, 8,O7\n\t"
            "OR    $dst,O7,$dst\n\t"
            "SRLX  $dst,16,O7\n\t"
            "OR    $dst,O7,$dst\n\t"
            "SRLX  $dst,32,O7\n\t"
            "OR    $dst,O7,$dst\t! replicate8B" %}
  ins_encode( enc_repl8b(src, dst));
  ins_pipe(ialu_reg);
%}

// Replicate scalar to packed byte values in Double register
instruct Repl8B_reg(stackSlotD dst, iRegI src) %{
  match(Set dst (Replicate8B src));
  expand %{
    iRegL tmp;
    Repl8B_reg_helper(tmp, src);
    regL_to_stkD(dst, tmp);
  %}
%}

// Replicate scalar constant to packed byte values in Double register
instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{
  match(Set dst (Replicate8B src));
#ifdef _LP64
  size(36);
#else
  size(8);
#endif
  format %{ "SETHI  hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t"
            "LDDF   [$tmp+lo(&Repl8($src))],$dst" %}
  ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) );
  ins_pipe(loadConFD);
%}

// Replicate scalar to packed char values into stack slot
instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{
  effect(DEF dst, USE src);
  format %{ "SLLX  $src,48,$dst\n\t"
            "SRLX  $dst,16,O7\n\t"
            "OR    $dst,O7,$dst\n\t"
            "SRLX  $dst,32,O7\n\t"
            "OR    $dst,O7,$dst\t! replicate4C" %}
  ins_encode( enc_repl4s(src, dst) );
  ins_pipe(ialu_reg);
%}

// Replicate scalar to packed char values into stack slot
instruct Repl4C_reg(stackSlotD dst, iRegI src) %{
  match(Set dst (Replicate4C src));
  expand %{
    iRegL tmp;
    Repl4C_reg_helper(tmp, src);
    regL_to_stkD(dst, tmp);
  %}
%}

// Replicate scalar constant to packed char values in Double register
instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{
  match(Set dst (Replicate4C src));
#ifdef _LP64
  size(36);
#else
  size(8);
#endif
  format %{ "SETHI  hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t"
            "LDDF   [$tmp+lo(&Repl4($src))],$dst" %}
  ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
  ins_pipe(loadConFD);
%}

// Replicate scalar to packed short values into stack slot
instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{
  effect(DEF dst, USE src);
  format %{ "SLLX  $src,48,$dst\n\t"
            "SRLX  $dst,16,O7\n\t"
            "OR    $dst,O7,$dst\n\t"
            "SRLX  $dst,32,O7\n\t"
            "OR    $dst,O7,$dst\t! replicate4S" %}
  ins_encode( enc_repl4s(src, dst) );
  ins_pipe(ialu_reg);
%}

// Replicate scalar to packed short values into stack slot
instruct Repl4S_reg(stackSlotD dst, iRegI src) %{
  match(Set dst (Replicate4S src));
  expand %{
    iRegL tmp;
    Repl4S_reg_helper(tmp, src);
    regL_to_stkD(dst, tmp);
  %}
%}

// Replicate scalar constant to packed short values in Double register
instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{
  match(Set dst (Replicate4S src));
#ifdef _LP64
  size(36);
#else
  size(8);
#endif
  format %{ "SETHI  hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t"
            "LDDF   [$tmp+lo(&Repl4($src))],$dst" %}
  ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) );
  ins_pipe(loadConFD);
%}

// Replicate scalar to packed int values in Double register
instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{
  effect(DEF dst, USE src);
  format %{ "SLLX  $src,32,$dst\n\t"
            "SRLX  $dst,32,O7\n\t"
            "OR    $dst,O7,$dst\t! replicate2I" %}
  ins_encode( enc_repl2i(src, dst));
  ins_pipe(ialu_reg);
%}

// Replicate scalar to packed int values in Double register
instruct Repl2I_reg(stackSlotD dst, iRegI src) %{
  match(Set dst (Replicate2I src));
  expand %{
    iRegL tmp;
    Repl2I_reg_helper(tmp, src);
    regL_to_stkD(dst, tmp);
  %}
%}

// Replicate scalar zero constant to packed int values in Double register
instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{
  match(Set dst (Replicate2I src));
#ifdef _LP64
  size(36);
#else
  size(8);
#endif
  format %{ "SETHI  hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t"
            "LDDF   [$tmp+lo(&Repl2($src))],$dst" %}
  ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) );
  ins_pipe(loadConFD);
%}

//----------Control Flow Instructions------------------------------------------
// Compare Instructions
// Compare Integers
instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
  match(Set icc (CmpI op1 op2));
  effect( DEF icc, USE op1, USE op2 );

  size(4);
  format %{ "CMP    $op1,$op2" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
  match(Set icc (CmpU op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! unsigned" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
  match(Set icc (CmpI op1 op2));
  effect( DEF icc, USE op1 );

  size(4);
  format %{ "CMP    $op1,$op2" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_imm);
%}

instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
  match(Set icc (CmpI (AndI op1 op2) zero));

  size(4);
  format %{ "BTST   $op2,$op1" %}
  opcode(Assembler::andcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg_zero);
%}

instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
  match(Set icc (CmpI (AndI op1 op2) zero));

  size(4);
  format %{ "BTST   $op2,$op1" %}
  opcode(Assembler::andcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_imm_zero);
%}

instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
  match(Set xcc (CmpL op1 op2));
  effect( DEF xcc, USE op1, USE op2 );

  size(4);
  format %{ "CMP    $op1,$op2\t\t! long" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
  match(Set xcc (CmpL op1 con));
  effect( DEF xcc, USE op1, USE con );

  size(4);
  format %{ "CMP    $op1,$con\t\t! long" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
  match(Set xcc (CmpL (AndL op1 op2) zero));
  effect( DEF xcc, USE op1, USE op2 );

  size(4);
  format %{ "BTST   $op1,$op2\t\t! long" %}
  opcode(Assembler::andcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

// useful for checking the alignment of a pointer:
instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
  match(Set xcc (CmpL (AndL op1 con) zero));
  effect( DEF xcc, USE op1, USE con );

  size(4);
  format %{ "BTST   $op1,$con\t\t! long" %}
  opcode(Assembler::andcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{
  match(Set icc (CmpU op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! unsigned" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_imm);
%}

// Compare Pointers
instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
  match(Set pcc (CmpP op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! ptr" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
  match(Set pcc (CmpP op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! ptr" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_imm);
%}

8547 8548 8549 8550 8551 8552 8553 8554 8555 8556 8557 8558 8559 8560 8561 8562 8563 8564 8565 8566 8567
// Compare Narrow oops
instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
  match(Set icc (CmpN op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! compressed ptr" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_reg);
%}

instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
  match(Set icc (CmpN op1 op2));

  size(4);
  format %{ "CMP    $op1,$op2\t! compressed ptr" %}
  opcode(Assembler::subcc_op3, Assembler::arith_op);
  ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
  ins_pipe(ialu_cconly_reg_imm);
%}

D
duke 已提交
8568 8569 8570 8571 8572 8573 8574 8575 8576 8577 8578 8579 8580 8581 8582 8583 8584 8585 8586 8587 8588 8589 8590 8591 8592 8593 8594 8595 8596 8597 8598 8599 8600 8601 8602 8603 8604 8605 8606 8607 8608 8609 8610 8611 8612 8613 8614 8615 8616 8617 8618 8619 8620 8621 8622 8623 8624 8625 8626 8627 8628 8629 8630 8631 8632 8633 8634 8635 8636 8637 8638 8639 8640 8641 8642 8643 8644 8645 8646 8647 8648 8649 8650 8651 8652 8653 8654 8655 8656 8657 8658 8659 8660 8661 8662 8663 8664 8665 8666 8667 8668 8669 8670 8671 8672 8673 8674 8675 8676 8677 8678 8679 8680 8681 8682 8683 8684 8685 8686 8687 8688 8689 8690 8691 8692 8693 8694 8695 8696 8697 8698 8699 8700 8701 8702 8703 8704 8705 8706 8707 8708 8709 8710 8711 8712 8713 8714 8715 8716 8717 8718 8719 8720 8721 8722 8723 8724 8725 8726 8727 8728 8729 8730 8731 8732 8733 8734 8735 8736 8737 8738 8739 8740 8741 8742 8743 8744 8745 8746 8747 8748 8749 8750 8751 8752 8753 8754 8755 8756 8757 8758 8759 8760 8761 8762 8763 8764 8765 8766 8767 8768 8769 8770 8771 8772 8773 8774 8775 8776 8777 8778 8779 8780 8781 8782 8783 8784 8785 8786 8787 8788 8789 8790 8791 8792 8793 8794 8795 8796 8797 8798 8799 8800 8801 8802 8803 8804 8805 8806 8807 8808 8809 8810 8811 8812 8813 8814 8815 8816 8817 8818 8819 8820 8821 8822 8823 8824 8825 8826 8827 8828 8829 8830 8831 8832 8833 8834 8835 8836 8837 8838 8839 8840 8841 8842 8843 8844 8845 8846 8847 8848 8849 8850 8851 8852 8853 8854 8855 8856 8857 8858 8859 8860 8861 8862 8863 8864 8865 8866 8867 8868 8869 8870 8871 8872 8873 8874 8875 8876 8877 8878 8879 8880 8881 8882 8883 8884 8885 8886 8887 8888 8889 8890 8891 8892 8893 8894 8895 8896 8897
//----------Max and Min--------------------------------------------------------
// Min Instructions
// Conditional move for min
instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
  effect( USE_DEF op2, USE op1, USE icc );

  size(4);
  format %{ "MOVlt  icc,$op1,$op2\t! min" %}
  opcode(Assembler::less);
  ins_encode( enc_cmov_reg_minmax(op2,op1) );
  ins_pipe(ialu_reg_flags);
%}

// Min Register with Register.
instruct minI_eReg(iRegI op1, iRegI op2) %{
  match(Set op2 (MinI op1 op2));
  ins_cost(DEFAULT_COST*2);
  expand %{
    flagsReg icc;
    compI_iReg(icc,op1,op2);
    cmovI_reg_lt(op2,op1,icc);
  %}
%}

// Max Instructions
// Conditional move for max
instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
  effect( USE_DEF op2, USE op1, USE icc );
  format %{ "MOVgt  icc,$op1,$op2\t! max" %}
  opcode(Assembler::greater);
  ins_encode( enc_cmov_reg_minmax(op2,op1) );
  ins_pipe(ialu_reg_flags);
%}

// Max Register with Register
instruct maxI_eReg(iRegI op1, iRegI op2) %{
  match(Set op2 (MaxI op1 op2));
  ins_cost(DEFAULT_COST*2);
  expand %{
    flagsReg icc;
    compI_iReg(icc,op1,op2);
    cmovI_reg_gt(op2,op1,icc);
  %}
%}


//----------Float Compares----------------------------------------------------
// Compare floating, generate condition code
instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
  match(Set fcc (CmpF src1 src2));

  size(4);
  format %{ "FCMPs  $fcc,$src1,$src2" %}
  opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
  ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
  ins_pipe(faddF_fcc_reg_reg_zero);
%}

instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
  match(Set fcc (CmpD src1 src2));

  size(4);
  format %{ "FCMPd  $fcc,$src1,$src2" %}
  opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
  ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
  ins_pipe(faddD_fcc_reg_reg_zero);
%}


// Compare floating, generate -1,0,1
instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
  match(Set dst (CmpF3 src1 src2));
  effect(KILL fcc0);
  ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
  format %{ "fcmpl  $dst,$src1,$src2" %}
  // Primary = float
  opcode( true );
  ins_encode( floating_cmp( dst, src1, src2 ) );
  ins_pipe( floating_cmp );
%}

instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
  match(Set dst (CmpD3 src1 src2));
  effect(KILL fcc0);
  ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
  format %{ "dcmpl  $dst,$src1,$src2" %}
  // Primary = double (not float)
  opcode( false );
  ins_encode( floating_cmp( dst, src1, src2 ) );
  ins_pipe( floating_cmp );
%}

//----------Branches---------------------------------------------------------
// Jump
// (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
  match(Jump switch_val);

  ins_cost(350);

  format %{  "SETHI  [hi(table_base)],O7\n\t"
             "ADD    O7, lo(table_base), O7\n\t"
             "LD     [O7+$switch_val], O7\n\t"
             "JUMP   O7"
         %}
  ins_encode( jump_enc( switch_val, table) );
  ins_pc_relative(1);
  ins_pipe(ialu_reg_reg);
%}

// Direct Branch.  Use V8 version with longer range.
instruct branch(label labl) %{
  match(Goto);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BA     $labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond
  opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always);
  ins_encode( enc_ba( labl ) );
  ins_pc_relative(1);
  ins_pipe(br);
%}

// Conditional Direct Branch
instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
  match(If cmp icc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BP$cmp   $icc,$labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bp( labl, cmp, icc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

// Branch-on-register tests all 64 bits.  We assume that values
// in 64-bit registers always remains zero or sign extended
// unless our code munges the high bits.  Interrupts can chop
// the high order bits to zero or sign at any time.
instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
  match(If cmp (CmpI op1 zero));
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BR$cmp   $op1,$labl" %}
  ins_encode( enc_bpr( labl, cmp, op1 ) );
  ins_pc_relative(1);
  ins_pipe(br_reg);
%}

instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
  match(If cmp (CmpP op1 null));
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BR$cmp   $op1,$labl" %}
  ins_encode( enc_bpr( labl, cmp, op1 ) );
  ins_pc_relative(1);
  ins_pipe(br_reg);
%}

instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
  match(If cmp (CmpL op1 zero));
  predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BR$cmp   $op1,$labl" %}
  ins_encode( enc_bpr( labl, cmp, op1 ) );
  ins_pc_relative(1);
  ins_pipe(br_reg);
%}

instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
  match(If cmp icc);
  effect(USE labl);

  format %{ "BP$cmp  $icc,$labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bp( labl, cmp, icc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
  match(If cmp pcc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BP$cmp  $pcc,$labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bpx( labl, cmp, pcc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
  match(If cmp fcc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "FBP$cmp $fcc,$labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_fbp( labl, cmp, fcc ) );
  ins_pc_relative(1);
  ins_pipe(br_fcc);
%}

instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
  match(CountedLoopEnd cmp icc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bp( labl, cmp, icc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
  match(CountedLoopEnd cmp icc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bp( labl, cmp, icc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

// ============================================================================
// Long Compare
//
// Currently we hold longs in 2 registers.  Comparing such values efficiently
// is tricky.  The flavor of compare used depends on whether we are testing
// for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
// The GE test is the negated LT test.  The LE test can be had by commuting
// the operands (yielding a GE test) and then negating; negate again for the
// GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
// NE test is negated from that.

// Due to a shortcoming in the ADLC, it mixes up expressions like:
// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
// difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
// are collapsed internally in the ADLC's dfa-gen code.  The match for
// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
// foo match ends up with the wrong leaf.  One fix is to not match both
// reg-reg and reg-zero forms of long-compare.  This is unfortunate because
// both forms beat the trinary form of long-compare and both are very useful
// on Intel which has so few registers.

instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
  match(If cmp xcc);
  effect(USE labl);

  size(8);
  ins_cost(BRANCH_COST);
  format %{ "BP$cmp   $xcc,$labl" %}
  // Prim = bits 24-22, Secnd = bits 31-30
  ins_encode( enc_bpl( labl, cmp, xcc ) );
  ins_pc_relative(1);
  ins_pipe(br_cc);
%}

// Manifest a CmpL3 result in an integer register.  Very painful.
// This is the test to avoid.
instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
  match(Set dst (CmpL3 src1 src2) );
  effect( KILL ccr );
  ins_cost(6*DEFAULT_COST);
  size(24);
  format %{ "CMP    $src1,$src2\t\t! long\n"
          "\tBLT,a,pn done\n"
          "\tMOV    -1,$dst\t! delay slot\n"
          "\tBGT,a,pn done\n"
          "\tMOV    1,$dst\t! delay slot\n"
          "\tCLR    $dst\n"
    "done:"     %}
  ins_encode( cmpl_flag(src1,src2,dst) );
  ins_pipe(cmpL_reg);
%}

// Conditional move
instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
  match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
  match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
  match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
  match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_imm);
%}

8898 8899 8900 8901 8902 8903 8904 8905
instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
  match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_reg);
%}

D
duke 已提交
8906 8907 8908 8909 8910 8911 8912 8913 8914 8915 8916 8917 8918 8919 8920 8921 8922 8923 8924 8925 8926 8927 8928 8929 8930 8931 8932 8933 8934 8935 8936 8937 8938 8939 8940 8941 8942 8943 8944 8945 8946 8947 8948 8949 8950 8951 8952 8953 8954 8955 8956 8957 8958 8959 8960 8961 8962 8963 8964 8965 8966 8967 8968 8969 8970 8971 8972 8973 8974 8975 8976 8977 8978 8979 8980 8981 8982 8983 8984 8985 8986 8987 8988 8989 8990 8991 8992 8993 8994 8995 8996 8997 8998 8999 9000 9001 9002 9003 9004 9005 9006 9007 9008 9009 9010 9011 9012 9013 9014 9015 9016 9017 9018 9019 9020 9021 9022 9023 9024 9025 9026 9027 9028 9029 9030 9031 9032 9033 9034 9035 9036 9037 9038 9039 9040 9041 9042 9043 9044 9045 9046 9047 9048 9049 9050 9051 9052 9053 9054 9055 9056 9057 9058 9059 9060 9061 9062 9063 9064 9065 9066 9067 9068 9069 9070 9071 9072 9073 9074 9075 9076 9077 9078 9079 9080 9081 9082 9083 9084 9085 9086 9087 9088 9089 9090 9091 9092 9093 9094 9095 9096 9097 9098 9099 9100 9101 9102 9103 9104 9105 9106 9107 9108 9109 9110 9111 9112 9113 9114 9115 9116 9117 9118 9119 9120 9121 9122 9123 9124 9125 9126 9127 9128 9129 9130 9131 9132 9133 9134 9135
instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
  match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
  ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_reg);
%}

instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
  match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
  ins_cost(140);
  format %{ "MOV$cmp  $xcc,$src,$dst" %}
  ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(ialu_imm);
%}

instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
  match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  opcode(0x101);
  format %{ "FMOVS$cmp $xcc,$src,$dst" %}
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(int_conditional_float_move);
%}

instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
  match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
  ins_cost(150);
  opcode(0x102);
  format %{ "FMOVD$cmp $xcc,$src,$dst" %}
  ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
  ins_pipe(int_conditional_float_move);
%}

// ============================================================================
// Safepoint Instruction
instruct safePoint_poll(iRegP poll) %{
  match(SafePoint poll);
  effect(USE poll);

  size(4);
#ifdef _LP64
  format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
#else
  format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
#endif
  ins_encode %{
    __ relocate(relocInfo::poll_type);
    __ ld_ptr($poll$$Register, 0, G0);
  %}
  ins_pipe(loadPollP);
%}

// ============================================================================
// Call Instructions
// Call Java Static Instruction
instruct CallStaticJavaDirect( method meth ) %{
  match(CallStaticJava);
  effect(USE meth);

  size(8);
  ins_cost(CALL_COST);
  format %{ "CALL,static  ; NOP ==> " %}
  ins_encode( Java_Static_Call( meth ), call_epilog );
  ins_pc_relative(1);
  ins_pipe(simple_call);
%}

// Call Java Dynamic Instruction
instruct CallDynamicJavaDirect( method meth ) %{
  match(CallDynamicJava);
  effect(USE meth);

  ins_cost(CALL_COST);
  format %{ "SET    (empty),R_G5\n\t"
            "CALL,dynamic  ; NOP ==> " %}
  ins_encode( Java_Dynamic_Call( meth ), call_epilog );
  ins_pc_relative(1);
  ins_pipe(call);
%}

// Call Runtime Instruction
instruct CallRuntimeDirect(method meth, l7RegP l7) %{
  match(CallRuntime);
  effect(USE meth, KILL l7);
  ins_cost(CALL_COST);
  format %{ "CALL,runtime" %}
  ins_encode( Java_To_Runtime( meth ),
              call_epilog, adjust_long_from_native_call );
  ins_pc_relative(1);
  ins_pipe(simple_call);
%}

// Call runtime without safepoint - same as CallRuntime
instruct CallLeafDirect(method meth, l7RegP l7) %{
  match(CallLeaf);
  effect(USE meth, KILL l7);
  ins_cost(CALL_COST);
  format %{ "CALL,runtime leaf" %}
  ins_encode( Java_To_Runtime( meth ),
              call_epilog,
              adjust_long_from_native_call );
  ins_pc_relative(1);
  ins_pipe(simple_call);
%}

// Call runtime without safepoint - same as CallLeaf
instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
  match(CallLeafNoFP);
  effect(USE meth, KILL l7);
  ins_cost(CALL_COST);
  format %{ "CALL,runtime leaf nofp" %}
  ins_encode( Java_To_Runtime( meth ),
              call_epilog,
              adjust_long_from_native_call );
  ins_pc_relative(1);
  ins_pipe(simple_call);
%}

// Tail Call; Jump from runtime stub to Java code.
// Also known as an 'interprocedural jump'.
// Target of jump will eventually return to caller.
// TailJump below removes the return address.
instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
  match(TailCall jump_target method_oop );

  ins_cost(CALL_COST);
  format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
  ins_encode(form_jmpl(jump_target));
  ins_pipe(tail_call);
%}


// Return Instruction
instruct Ret() %{
  match(Return);

  // The epilogue node did the ret already.
  size(0);
  format %{ "! return" %}
  ins_encode();
  ins_pipe(empty);
%}


// Tail Jump; remove the return address; jump to target.
// TailCall above leaves the return address around.
// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
// "restore" before this instruction (in Epilogue), we need to materialize it
// in %i0.
instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
  match( TailJump jump_target ex_oop );
  ins_cost(CALL_COST);
  format %{ "! discard R_O7\n\t"
            "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
  ins_encode(form_jmpl_set_exception_pc(jump_target));
  // opcode(Assembler::jmpl_op3, Assembler::arith_op);
  // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
  // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
  ins_pipe(tail_call);
%}

// Create exception oop: created by stack-crawling runtime code.
// Created exception is now available to this handler, and is setup
// just prior to jumping to this handler.  No code emitted.
instruct CreateException( o0RegP ex_oop )
%{
  match(Set ex_oop (CreateEx));
  ins_cost(0);

  size(0);
  // use the following format syntax
  format %{ "! exception oop is in R_O0; no code emitted" %}
  ins_encode();
  ins_pipe(empty);
%}


// Rethrow exception:
// The exception oop will come in the first argument position.
// Then JUMP (not call) to the rethrow stub code.
instruct RethrowException()
%{
  match(Rethrow);
  ins_cost(CALL_COST);

  // use the following format syntax
  format %{ "Jmp    rethrow_stub" %}
  ins_encode(enc_rethrow);
  ins_pipe(tail_call);
%}


// Die now
instruct ShouldNotReachHere( )
%{
  match(Halt);
  ins_cost(CALL_COST);

  size(4);
  // Use the following format syntax
  format %{ "ILLTRAP   ; ShouldNotReachHere" %}
  ins_encode( form2_illtrap() );
  ins_pipe(tail_call);
%}

// ============================================================================
// The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
// array for an instance of the superklass.  Set a hidden internal cache on a
// hit (cache is checked with exposed code in gen_subtype_check()).  Return
// not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
  match(Set index (PartialSubtypeCheck sub super));
  effect( KILL pcc, KILL o7 );
  ins_cost(DEFAULT_COST*10);
  format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
  ins_encode( enc_PartialSubtypeCheck() );
  ins_pipe(partial_subtype_check_pipe);
%}

instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
  match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
  effect( KILL idx, KILL o7 );
  ins_cost(DEFAULT_COST*10);
  format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
  ins_encode( enc_PartialSubtypeCheck() );
  ins_pipe(partial_subtype_check_pipe);
%}

9136

D
duke 已提交
9137 9138 9139 9140 9141 9142 9143 9144 9145 9146 9147 9148 9149 9150 9151 9152 9153 9154 9155 9156 9157 9158 9159 9160 9161 9162 9163 9164 9165 9166 9167 9168 9169 9170 9171 9172 9173 9174 9175 9176 9177
// ============================================================================
// inlined locking and unlocking

instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
  match(Set pcc (FastLock object box));

  effect(KILL scratch, TEMP scratch2);
  ins_cost(100);

  size(4*112);       // conservative overestimation ...
  format %{ "FASTLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
  ins_encode( Fast_Lock(object, box, scratch, scratch2) );
  ins_pipe(long_memory_op);
%}


instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{
  match(Set pcc (FastUnlock object box));
  effect(KILL scratch, TEMP scratch2);
  ins_cost(100);

  size(4*120);       // conservative overestimation ...
  format %{ "FASTUNLOCK  $object, $box; KILL $scratch, $scratch2, $box" %}
  ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
  ins_pipe(long_memory_op);
%}

// Count and Base registers are fixed because the allocator cannot
// kill unknown registers.  The encodings are generic.
instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
  match(Set dummy (ClearArray cnt base));
  effect(TEMP temp, KILL ccr);
  ins_cost(300);
  format %{ "MOV    $cnt,$temp\n"
    "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
    "        BRge   loop\t\t! Clearing loop\n"
    "        STX    G0,[$base+$temp]\t! delay slot" %}
  ins_encode( enc_Clear_Array(cnt, base, temp) );
  ins_pipe(long_memory_op);
%}

9178 9179
instruct string_compare(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
                        o7RegI tmp3, flagsReg ccr) %{
D
duke 已提交
9180
  match(Set result (StrComp str1 str2));
9181
  effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
D
duke 已提交
9182 9183 9184 9185 9186 9187
  ins_cost(300);
  format %{ "String Compare $str1,$str2 -> $result" %}
  ins_encode( enc_String_Compare(str1, str2, tmp1, tmp2, result) );
  ins_pipe(long_memory_op);
%}

C
cfang 已提交
9188 9189 9190 9191 9192 9193 9194 9195 9196 9197 9198 9199 9200 9201 9202 9203 9204 9205 9206
instruct string_equals(o0RegP str1, o1RegP str2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
                       o7RegI tmp3, flagsReg ccr) %{
  match(Set result (StrEquals str1 str2));
  effect(USE_KILL str1, USE_KILL str2, KILL tmp1, KILL tmp2, KILL ccr, KILL tmp3);
  ins_cost(300);
  format %{ "String Equals $str1,$str2 -> $result" %}
  ins_encode( enc_String_Equals(str1, str2, tmp1, tmp2, result) );
  ins_pipe(long_memory_op);
%}

instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, g4RegP tmp2, notemp_iRegI result,
                        flagsReg ccr) %{
  match(Set result (AryEq ary1 ary2));
  effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
  ins_cost(300);
  format %{ "Array Equals $ary1,$ary2 -> $result" %}
  ins_encode( enc_Array_Equals(ary1, ary2, tmp1, tmp2, result));
  ins_pipe(long_memory_op);
%}
9207

9208 9209 9210 9211 9212 9213 9214 9215 9216 9217 9218 9219 9220 9221 9222 9223 9224 9225 9226 9227 9228 9229 9230 9231 9232 9233 9234 9235 9236 9237 9238 9239 9240 9241 9242 9243 9244 9245 9246 9247 9248 9249 9250 9251 9252 9253 9254 9255 9256 9257 9258 9259 9260 9261 9262 9263 9264 9265 9266 9267 9268 9269 9270 9271 9272 9273 9274 9275 9276 9277 9278 9279 9280 9281 9282 9283 9284 9285 9286 9287 9288 9289 9290 9291 9292 9293 9294 9295 9296 9297 9298 9299 9300 9301 9302 9303 9304 9305 9306 9307 9308 9309 9310 9311 9312 9313 9314 9315 9316 9317 9318 9319 9320 9321 9322 9323 9324 9325 9326 9327 9328 9329 9330 9331 9332 9333 9334 9335 9336 9337 9338 9339 9340 9341 9342 9343 9344 9345 9346

//---------- Zeros Count Instructions ------------------------------------------

instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
  match(Set dst (CountLeadingZerosI src));
  effect(TEMP dst, TEMP tmp, KILL cr);

  // x |= (x >> 1);
  // x |= (x >> 2);
  // x |= (x >> 4);
  // x |= (x >> 8);
  // x |= (x >> 16);
  // return (WORDBITS - popc(x));
  format %{ "SRL     $src,1,$dst\t! count leading zeros (int)\n\t"
            "OR      $src,$tmp,$dst\n\t"
            "SRL     $dst,2,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRL     $dst,4,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRL     $dst,8,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRL     $dst,16,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "POPC    $dst,$dst\n\t"
            "MOV     32,$tmp\n\t"
            "SUB     $tmp,$dst,$dst" %}
  ins_encode %{
    Register Rdst = $dst$$Register;
    Register Rsrc = $src$$Register;
    Register Rtmp = $tmp$$Register;
    __ srl(Rsrc, 1, Rtmp);
    __ or3(Rsrc, Rtmp, Rdst);
    __ srl(Rdst, 2, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srl(Rdst, 4, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srl(Rdst, 8, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srl(Rdst, 16, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ popc(Rdst, Rdst);
    __ mov(BitsPerInt, Rtmp);
    __ sub(Rtmp, Rdst, Rdst);
  %}
  ins_pipe(ialu_reg);
%}

instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
  match(Set dst (CountLeadingZerosL src));
  effect(TEMP dst, TEMP tmp, KILL cr);

  // x |= (x >> 1);
  // x |= (x >> 2);
  // x |= (x >> 4);
  // x |= (x >> 8);
  // x |= (x >> 16);
  // x |= (x >> 32);
  // return (WORDBITS - popc(x));
  format %{ "SRLX    $src,1,$dst\t! count leading zeros (long)\n\t"
            "OR      $src,$tmp,$dst\n\t"
            "SRLX    $dst,2,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRLX    $dst,4,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRLX    $dst,8,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRLX    $dst,16,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "SRLX    $dst,32,$tmp\n\t"
            "OR      $dst,$tmp,$dst\n\t"
            "POPC    $dst,$dst\n\t"
            "MOV     64,$tmp\n\t"
            "SUB     $tmp,$dst,$dst" %}
  ins_encode %{
    Register Rdst = $dst$$Register;
    Register Rsrc = $src$$Register;
    Register Rtmp = $tmp$$Register;
    __ srlx(Rsrc, 1, Rtmp);
    __ or3(Rsrc, Rtmp, Rdst);
    __ srlx(Rdst, 2, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srlx(Rdst, 4, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srlx(Rdst, 8, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srlx(Rdst, 16, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ srlx(Rdst, 32, Rtmp);
    __ or3(Rdst, Rtmp, Rdst);
    __ popc(Rdst, Rdst);
    __ mov(BitsPerLong, Rtmp);
    __ sub(Rtmp, Rdst, Rdst);
  %}
  ins_pipe(ialu_reg);
%}

instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
  match(Set dst (CountTrailingZerosI src));
  effect(TEMP dst, KILL cr);

  // return popc(~x & (x - 1));
  format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
            "ANDN    $dst,$src,$dst\n\t"
            "SRL     $dst,R_G0,$dst\n\t"
            "POPC    $dst,$dst" %}
  ins_encode %{
    Register Rdst = $dst$$Register;
    Register Rsrc = $src$$Register;
    __ sub(Rsrc, 1, Rdst);
    __ andn(Rdst, Rsrc, Rdst);
    __ srl(Rdst, G0, Rdst);
    __ popc(Rdst, Rdst);
  %}
  ins_pipe(ialu_reg);
%}

instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{
  predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
  match(Set dst (CountTrailingZerosL src));
  effect(TEMP dst, KILL cr);

  // return popc(~x & (x - 1));
  format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
            "ANDN    $dst,$src,$dst\n\t"
            "POPC    $dst,$dst" %}
  ins_encode %{
    Register Rdst = $dst$$Register;
    Register Rsrc = $src$$Register;
    __ sub(Rsrc, 1, Rdst);
    __ andn(Rdst, Rsrc, Rdst);
    __ popc(Rdst, Rdst);
  %}
  ins_pipe(ialu_reg);
%}


9347 9348 9349 9350 9351 9352 9353 9354 9355 9356 9357 9358 9359 9360 9361 9362 9363 9364 9365 9366 9367 9368 9369 9370 9371 9372
//---------- Population Count Instructions -------------------------------------

instruct popCountI(iRegI dst, iRegI src) %{
  predicate(UsePopCountInstruction);
  match(Set dst (PopCountI src));

  format %{ "POPC   $src, $dst" %}
  ins_encode %{
    __ popc($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}

// Note: Long.bitCount(long) returns an int.
instruct popCountL(iRegI dst, iRegL src) %{
  predicate(UsePopCountInstruction);
  match(Set dst (PopCountL src));

  format %{ "POPC   $src, $dst" %}
  ins_encode %{
    __ popc($src$$Register, $dst$$Register);
  %}
  ins_pipe(ialu_reg);
%}


D
duke 已提交
9373 9374 9375 9376 9377 9378 9379 9380 9381 9382 9383 9384 9385 9386 9387 9388 9389 9390 9391 9392 9393 9394 9395 9396 9397 9398 9399 9400 9401 9402 9403 9404 9405 9406 9407 9408 9409 9410 9411 9412 9413 9414 9415 9416 9417 9418 9419 9420 9421 9422 9423 9424 9425 9426 9427 9428 9429 9430 9431 9432 9433 9434 9435 9436 9437 9438 9439 9440 9441 9442 9443 9444 9445 9446 9447 9448 9449 9450 9451 9452 9453 9454 9455 9456 9457 9458 9459 9460 9461 9462
// ============================================================================
//------------Bytes reverse--------------------------------------------------

instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
  match(Set dst (ReverseBytesI src));
  effect(DEF dst, USE src);

  // Op cost is artificially doubled to make sure that load or store
  // instructions are preferred over this one which requires a spill
  // onto a stack slot.
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
  opcode(Assembler::lduwa_op3);
  ins_encode( form3_mem_reg_little(src, dst) );
  ins_pipe( iload_mem );
%}

instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
  match(Set dst (ReverseBytesL src));
  effect(DEF dst, USE src);

  // Op cost is artificially doubled to make sure that load or store
  // instructions are preferred over this one which requires a spill
  // onto a stack slot.
  ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDXA   $src, $dst\t!asi=primary_little" %}

  opcode(Assembler::ldxa_op3);
  ins_encode( form3_mem_reg_little(src, dst) );
  ins_pipe( iload_mem );
%}

// Load Integer reversed byte order
instruct loadI_reversed(iRegI dst, memory src) %{
  match(Set dst (ReverseBytesI (LoadI src)));

  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}

  opcode(Assembler::lduwa_op3);
  ins_encode( form3_mem_reg_little( src, dst) );
  ins_pipe(iload_mem);
%}

// Load Long - aligned and reversed
instruct loadL_reversed(iRegL dst, memory src) %{
  match(Set dst (ReverseBytesL (LoadL src)));

  ins_cost(DEFAULT_COST + MEMORY_REF_COST);
  size(8);
  format %{ "LDXA   $src, $dst\t!asi=primary_little" %}

  opcode(Assembler::ldxa_op3);
  ins_encode( form3_mem_reg_little( src, dst ) );
  ins_pipe(iload_mem);
%}

// Store Integer reversed byte order
instruct storeI_reversed(memory dst, iRegI src) %{
  match(Set dst (StoreI dst (ReverseBytesI src)));

  ins_cost(MEMORY_REF_COST);
  size(8);
  format %{ "STWA   $src, $dst\t!asi=primary_little" %}

  opcode(Assembler::stwa_op3);
  ins_encode( form3_mem_reg_little( dst, src) );
  ins_pipe(istore_mem_reg);
%}

// Store Long reversed byte order
instruct storeL_reversed(memory dst, iRegL src) %{
  match(Set dst (StoreL dst (ReverseBytesL src)));

  ins_cost(MEMORY_REF_COST);
  size(8);
  format %{ "STXA   $src, $dst\t!asi=primary_little" %}

  opcode(Assembler::stxa_op3);
  ins_encode( form3_mem_reg_little( dst, src) );
  ins_pipe(istore_mem_reg);
%}

//----------PEEPHOLE RULES-----------------------------------------------------
// These must follow all instruction definitions as they use the names
// defined in the instructions definitions.
//
T
twisti 已提交
9463
// peepmatch ( root_instr_name [preceding_instruction]* );
D
duke 已提交
9464 9465 9466 9467 9468 9469 9470 9471 9472 9473 9474 9475 9476 9477 9478 9479 9480 9481 9482 9483 9484 9485 9486 9487 9488 9489 9490 9491 9492 9493 9494 9495 9496 9497 9498 9499 9500 9501 9502 9503 9504 9505 9506 9507 9508 9509 9510 9511 9512 9513 9514 9515 9516 9517 9518 9519 9520 9521 9522 9523 9524 9525 9526 9527 9528 9529 9530 9531 9532 9533 9534 9535 9536 9537
//
// peepconstraint %{
// (instruction_number.operand_name relational_op instruction_number.operand_name
//  [, ...] );
// // instruction numbers are zero-based using left to right order in peepmatch
//
// peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
// // provide an instruction_number.operand_name for each operand that appears
// // in the replacement instruction's match rule
//
// ---------VM FLAGS---------------------------------------------------------
//
// All peephole optimizations can be turned off using -XX:-OptoPeephole
//
// Each peephole rule is given an identifying number starting with zero and
// increasing by one in the order seen by the parser.  An individual peephole
// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
// on the command-line.
//
// ---------CURRENT LIMITATIONS----------------------------------------------
//
// Only match adjacent instructions in same basic block
// Only equality constraints
// Only constraints between operands, not (0.dest_reg == EAX_enc)
// Only one replacement instruction
//
// ---------EXAMPLE----------------------------------------------------------
//
// // pertinent parts of existing instructions in architecture description
// instruct movI(eRegI dst, eRegI src) %{
//   match(Set dst (CopyI src));
// %}
//
// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
//   match(Set dst (AddI dst src));
//   effect(KILL cr);
// %}
//
// // Change (inc mov) to lea
// peephole %{
//   // increment preceeded by register-register move
//   peepmatch ( incI_eReg movI );
//   // require that the destination register of the increment
//   // match the destination register of the move
//   peepconstraint ( 0.dst == 1.dst );
//   // construct a replacement instruction that sets
//   // the destination to ( move's source register + one )
//   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
// %}
//

// // Change load of spilled value to only a spill
// instruct storeI(memory mem, eRegI src) %{
//   match(Set mem (StoreI mem src));
// %}
//
// instruct loadI(eRegI dst, memory mem) %{
//   match(Set dst (LoadI mem));
// %}
//
// peephole %{
//   peepmatch ( loadI storeI );
//   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
//   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
// %}

//----------SMARTSPILL RULES---------------------------------------------------
// These must follow all instruction definitions as they use the names
// defined in the instructions definitions.
//
// SPARC will probably not have any of these rules due to RISC instruction set.

//----------PIPELINE-----------------------------------------------------------
// Rules which define the behavior of the target architectures pipeline.