Initial device tree support for Qualcomm MSM8994 SoC and
Huawei Angler / Google Nexus 6P support.

The device tree is based on the Google 3.10 kernel tree.

The device can be booted into the initrd with only one CPU running.
Signed-off-by: NBastian Köcher <mail@kchr.de>
[jeremymc@redhat.com: removed Kconfig, defconfig, move from Huawei to qcom dir]
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
Tested-by: NMichael Scott <michael.scott@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Initial device tree support for Qualcomm MSM8992 SoC and
LG Bullhead / Google Nexus 5X support.
Signed-off-by: NJeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add SMP2P and APCS DT nodes required for Qualcomm ADSP
Peripheral Image Loader.
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add SMEM and TCSR DT nodes on MSM8996.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add reserve-memory nodes required for Qualcomm
Peripheral Image Loaders
Acked-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add DT node to carveout memory for shared memory region.
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NSarangdhar Joshi <spjoshi@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch add support to Analog audio both Playback and Capture via
msm8916 WCD muti codec.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

pm8994 has 22 gpios, so add the missing interrupts entry for one
of the gpios
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

On the APQ8016 SBC, the LDO2 PM8916 regulator feeds 1.2V to the following:

- VDDA_1P2_MIPI_DSI and VDDA_MIPI_CSI pins on APQ8016.
- VCCCAD pins on the LPDDR3 chip.
- VDDPX_1 pins on APQ8016.

The LDO6 regulator feeds 1.8V to:
- VDAA_MIPI_DSI0_PLL pin on APQ8016.
- QFPROM_BLOW_VDD pin on PM8916.
- The AVDD, A2VDD and DVDD pins on ADV7533 bridge.

The LDO17 regulator feeds 3.3V to:
- The V3P3 pin on ADV7533 bridge.

Currently, the regulator min/max voltages for all the LDOs are set to the
range of what the PMIC supports. Set the ranges for L2, L6 and L17 to what
we need, i.e. 1.2V, 1.8V and 3.3V respectively.
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds pmic specific dts which are configured specially
for db820c. One of such pin is GPIO_F on the Low Speed expansion
which has default output voltage of 2.7v. This patch fixes setup
for that pin to have an output voltage of 1.8v to comply with
96boards LS expansion specs.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

The Hexagon core on the msm8916 provides services for audio control,
audio output, sensors and the Hexagon SDK. The Hexagon remoteproc node
allows us to boot this core.

Although its part of the core platform its left disabled as it will
crash without the rmtfs QMI service and we do not yet handle crashes
gracefully.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

Add the Hexagon SMD edge, so that QRTR is probed when the Hexagon is
booted.
Signed-off-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NAndy Gross <andy.gross@linaro.org>

This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.

[Sebastian: rename cache node from "l2-cache" to "cache"]
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

After commit f29a72c2 ("watchdog: dw_wdt: Convert to use watchdog
infrastructure"), the dw_wdt driver can support multiple variants, so
unconditionally enable all dw_wdt nodes now.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Commit ac82d127 ("arm64: perf: add Cortex-A53 support") adds the
cortex A53 PMU support, thus instead of using the generic armv8-pmuv3
compatibility use the more specific Cortex A53 compatibility.
Signed-off-by: NJisheng Zhang <jszhang@marvell.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>

Enable throttle function for SOC_THERM.
Set "hot" trips for cpu and gpu thermal zones, which
can trigger the SOC_THERM hardware throttle.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Set general "critical" trip temperatures for cpu, gpu, mem and pllx
thermal zones on Tegra210, these trips can trigger shut down or reset.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Adds soctherm node for Tegra210, and add cpu,
gpu, mem, pllx as thermal-zones. Set critical
trip temperatures for them.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Enable throttle function for SOC_THERM.
Set "hot" trips for cpu and gpu thermal zones, which
can trigger the SOC_THERM hardware throttle.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Set general "critical" trip temperatures for cpu, gpu, mem and pllx
thermal zones on Tegra132, these trips can trigger shut down or reset.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

The Tegra132 has the specific settings for soctherm,
so change to use campatible "nvidia,tegra132-soctherm" for it.
And adds cpu, gpu, mem and pllx thermal zones.
Signed-off-by: NWei Ni <wni@nvidia.com>
Signed-off-by: NZhang Rui <rui.zhang@intel.com>

Add device tree support for ZX296718 SoC and evaluation board based
on it.  Also document new values.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Enable both gxbb USB controller and add a 5V regulator for the OTG port
VBUS
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
[khilman: rename vbus node to match P200 schematics]
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add DT nodes to enable APM X-Gene 2 CPU clocks.

[dhdang: changelog]
Signed-off-by: NHoan Tran <hotran@apm.com>
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch adds DT node to enable hwmon driver for APM X-Gene SoC.
Signed-off-by: NHoan Tran <hotran@apm.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>

On X-Gene v1 and X-Gene v2, PCIe legacy interrupt
should be configured as level-active high.
Signed-off-by: NDuc Dang <dhdang@apm.com>

This patch adds APM X-Gene v2 SoC PMU DTS entries.
Signed-off-by: NDuc Dang <dhdang@apm.com>
Cc: Tai Nguyen <ttnguyen@apm.com>

This patch adds APM X-Gene SoC PMU DTS entries.
Signed-off-by: NTai Nguyen <ttnguyen@apm.com>

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: NDuc Dang <dhdang@apm.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the nodes for the dwc2 USB controller and the related USB PHYs.
Currently we force usb0 to host mode because OTG is currently not
working in our PHY driver.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Add nodes for i2c bus on gxbb based platforms.
On the OdroidC2 (I2C A) and P200 (I2C B), the pull-up resistor are
present directly on the board. This indicates that these pins are
dedicated to i2c.
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

This is used to configure the pins of the sd_emmc_a controller to
which an SDIO module is connected (when available).
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

The Amlogic reference driver uses the "mc_val" devicetree property to
configure the PRG_ETHERNET_ADDR0 register. Unfortunately it uses magic
values for this configuration.
According to the datasheet the PRG_ETHERNET_ADDR0 register is at address
0xc8834108. However, the reference driver uses 0xc8834540 instead.
According to my tests, the value from the reference driver is correct.

No changes are required to the board dts files because the only
required configuration option is the phy-mode, which had to be
configured correctly before as well.
Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Tested-by: NJérôme Brunet <jbrunet@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NKevin Hilman <khilman@baylibre.com>