1. 14 5月, 2014 1 次提交
  2. 01 5月, 2014 1 次提交
    • C
      gianfar: Avoid unnecessary reg accesses in adjust_link() · 6ce29b0e
      Claudiu Manoil 提交于
      For phy devices that don't issue interrupts upon link
      state changes, phylib polls the link state resulting in
      repeated calls to adjust_link(), even if the link state
      didn't change.  As a result, some mac registers are
      repeatedly read and written with the same values, which
      is not ok.
      
      To fix this, adjust_link() has been refactored to check
      first whether the link state has changed and to take action
      only if needed, updating mac registers and local state
      variables.  The 'new_state' local flag, set if one of the
      link params changed (link, speed or duplex), has been
      rendered useless and removed by this refactoring.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      6ce29b0e
  3. 25 4月, 2014 1 次提交
  4. 01 4月, 2014 1 次提交
  5. 28 3月, 2014 2 次提交
  6. 25 3月, 2014 2 次提交
  7. 24 3月, 2014 1 次提交
    • C
      gianfar: Fix P1010 config regression (SQ polling) · c65d7533
      Claudiu Manoil 提交于
      The P1010 device tree restricts the number of
      supported interrupt groups to 1, although the eth
      controller can support 2 interrupt groups and the
      driver assumes the Multi-Group mode ("fsl,etsec2" model).
      
      So, in this case the assumption that the Multi-Group
      mode (MQ_MG_MODE) devices always support 2 interrupt
      groups is false.  To fix this, a check for the actual
      number of interrupt groups enabled in the board's
      device tree has been added in gfar_probe for the
      "fsl,etsec2" devices.
      
      Without this fix, P1010 based boards claim support for
      2 Tx queues to the net stack but only one is actually
      allocated, leading to NULL access in xmit.  This issue
      was introduced by enabling Single-Queue polling for
      the P1010 devices.
      (71ff9e3d gianfar: Use Single-Queue polling for
      "fsl,etsec2")
      
      Fixes: 71ff9e3dSigned-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c65d7533
  8. 22 3月, 2014 1 次提交
  9. 15 3月, 2014 1 次提交
  10. 14 3月, 2014 1 次提交
  11. 13 3月, 2014 1 次提交
  12. 12 3月, 2014 1 次提交
  13. 11 3月, 2014 2 次提交
    • C
      gianfar: Use Single-Queue polling for "fsl,etsec2" · 71ff9e3d
      Claudiu Manoil 提交于
      For the "fsl,etsec2" compatible models the driver currently
      supports 8 Tx and Rx DMA rings (aka HW queues).  However, there
      are only 2 pairs of Rx/Tx interrupt lines, as these controllers
      are integrated in low power SoCs with 2 CPUs at most.  As a result,
      there are at most 2 NAPI instances that have to service multiple
      Tx and Rx queues for these devices.  This complicates the NAPI
      polling routine having to iterate over the mutiple Rx/Tx queues
      hooked to the same interrupt lines.  And there's also an overhead
      at HW level, as the controller needs to service all the 8 Tx rings
      in a round robin manner.  The combined overhead shows up for multi
      parallel Tx flows transmitted by the kernel stack, when the driver
      usually starts returning NETDEV_TX_BUSY leading to NETDEV WATCHDOG
      Tx timeout triggering if the Tx path is congested for too long.
      
      As an alternative, this patch makes the driver support only one
      Tx/Rx DMA ring per NAPI instance (per interrupt group or pair
      of Tx/Rx interrupt lines) by default.  The simplified single queue
      polling routine (gfar_poll_sq) will be the default napi poll routine
      for the etsec2 devices too.  Some adjustments needed to be made to
      link the Tx/Rx HW queues with each NAPI instance (2 in this case).
      The gfar_poll_sq() is already successfully used by older SQ_SG_MODE
      (single interrupt group) controllers.
      This patch fixes Tx timeout triggering under heavy Tx traffic load
      (i.e. iperf -c -P 8) for the "fsl,etsec2" (currently the only
      MQ_MG_MODE devices).  There's also a significant memory footprint
      reduction by supporting 2 Rx/Tx DMA rings (at most), instead of 8,
      for these devices.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      71ff9e3d
    • C
      gianfar: Separate out the Tx interrupt handling (Tx NAPI) · aeb12c5e
      Claudiu Manoil 提交于
      There are some concurrency issues on devices w/ 2 CPUs related
      to the handling of Rx and Tx interrupts.  eTSEC has separate
      interrupt lines for Rx and Tx but a single imask register
      to mask these interrupts and a single NAPI instance to handle
      both Rx and Tx work.  As a result, the Rx and Tx ISRs are
      identical, both are invoking gfar_schedule_cleanup(), however
      both handlers can be entered at the same time when the Rx and
      Tx interrupts are taken by different CPUs.  In this case
      spurrious interrupts (SPU) show up (in /proc/interrupts)
      indicating a concurrency issue.  Also, Tx overruns followed
      by Tx timeout have been observed under heavy Tx traffic load.
      
      To address these issues, the schedule cleanup ISR part has
      been changed to handle the Rx and Tx interrupts independently.
      The patch adds a separate NAPI poll routine for Tx cleanup to
      be triggerred independently by the Tx confirmation interrupts
      only.  Existing poll functions are modified to handle only
      the Rx path processing.  The Tx poll routine does not need a
      budget, since Tx processing doesn't consume NAPI budget, and
      hence it is registered with minimum NAPI weight.
      NAPI scheduling does not require locking since there are
      different NAPI instances between the Rx and Tx confirmation
      paths now.
      So, the patch fixes the occurence of spurrious Rx/Tx interrupts.
      Tx overruns also occur less frequently now.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      aeb12c5e
  14. 25 2月, 2014 5 次提交
    • C
      gianfar: Fix Tx int miss, dont write IC on-the-fly · f19015ba
      Claudiu Manoil 提交于
      Programming the interrupt coalescing (IC) registers while
      the controller/DMA is on may incur the loss of one Tx
      confirmation interrupt, under certain conditions.  This is
      a subtle hw race because it does not occur during a burst
      of Tx packets.  It has been observed on p2020 devices that,
      if just one packet is being xmit'ed, the Tx confirmation
      doesn't trigger and BQL evetually blocks the Tx queues,
      followed by Tx timeout and an un-responsive device.
      This issue was not apparent prior to introducing BQL
      support, as a late Tx confirmation was not an issue back then
      and the next burst of Tx frames would have triggered the
      Tx confirmation/ Tx ring cleanup anyway.
      
      Bottom line, the hw specifications state that the IC registers
      should not be programmed while the Rx/Tx blocks (the DMA) are
      enabled. Further more, these registers are currently re-written
      with the same values on the processing path, over and over again.
      To fix this, rewriting the IC registers has been removed from
      the processing path (napi poll).  A complete MAC reset procedure
      has been implemented for the ethtool -c option instead, to
      reliably update these registers while the controller is stopped.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      f19015ba
    • C
      gianfar: Fix device reset races (oops) for Tx · 0851133b
      Claudiu Manoil 提交于
      The device reset procedure, stop_gfar()/startup_gfar(), has
      concurrency issues.
      "Kernel access of bad area" oopses show up during Tx timeout
      device reset or other reset cases (like changing MTU) that
      happen while the interface still has traffic. The oopses
      happen in start_xmit and clean_tx_ring when accessing tx_queue->
      tx_skbuff which is NULL. The race comes from de-allocating the
      tx_skbuff while transmission and napi processing are still
      active. Though the Tx queues get temoprarily stopped when Tx
      timeout occurs, they get re-enabled as a result of Tx congestion
      handling inside the napi context (see clean_tx_ring()). Not
      disabling the napi during reset is also a bug, because
      clean_tx_ring() will try to access tx_skbuff while it is being
      de-alloc'ed and re-alloc'ed.
      
      To fix this, stop_gfar() needs to disable napi processing
      after stopping the Tx queues. However, in order to prevent
      clean_tx_ring() to re-enable the Tx queue before the napi
      gets disabled, the device state DOWN has been introduced.
      It prevents the Tx congestion management from re-enabling the
      de-congested Tx queue while the device is brought down.
      An additional locking state, RESETTING, has been introduced
      to prevent simultaneous resets or to prevent configuring the
      device while it is resetting.
      The bogus 'rxlock's (for each Rx queue) have been removed since
      their purpose is not justified, as they don't prevent nor are
      suited to prevent device reset/reconfig races (such as this one).
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      0851133b
    • C
      gianfar: Don't free/request irqs on device reset · 80ec396c
      Claudiu Manoil 提交于
      Resetting the device (stop_gfar()/startup_gfar()) should
      be fast and to the point, in order to timely recover
      from an error condition (like Tx timeout) or during
      device reconfig.  The irq free/ request routines are just
      redundant here, and they should be part of the device
      close/ open routines instead.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      80ec396c
    • C
      gianfar: Fix on-the-fly vlan and mtu updates · 88302648
      Claudiu Manoil 提交于
      The RCTRL and TCTRL registers should not be changed
      on-the-fly, while the controller is running, otherwise
      unexpected behaviour occurs.  But that's exactly what
      gfar_vlan_mode() does, updating the VLAN acceleration
      bits inside RCTRL/TCTRL.  The attempt to lock these
      operations doesn't help, but only adds to the confusion.
      There's also a dependency for Rx FCB insertion (activating
      /de-activating the TOE offload block on Rx) which might
      change the required rx buffer size.  This makes matters
      worse as gfar_vlan_mode() ends up calling gfar_change_mtu(),
      though the MTU size remains the same.  Note that there are
      other situations that may affect the required rx buffer size,
      like changing RXCSUM or rx hw timestamping, but errorneously
      the rx buffer size is not recomputed/ updated in the process.
      
      To fix this, do the vlan updates properly inside the MAC
      reset and reconfiguration procedure, which takes care of
      the rx buffer size dependecy and the rx TOE block (PRSDEP)
      activation/deactivation as well (in the correct order).
      As a consequence, MTU/ rx buff size updates are done now
      by the same MAC reset and reconfig procedure, so that out
      of context updates to MAXFRM, MRBLR, and MACCFG inside
      change_mtu() are no longer needed.  The rx buffer size
      dependecy to Rx FCB is now handled for the other cases too
      (RXCSUM and rx hw timestamping).
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      88302648
    • C
      gianfar: Implement MAC reset and reconfig procedure · a328ac92
      Claudiu Manoil 提交于
      The main MAC config registers like: RCTRL/TCTRL, MRBLR,
      MAXFRM, RXIC/TXIC, most fields of MACCFG1/2, should not
      be changed on-the-fly, but at least after stopping the
      DMA and disabling the Rx/Tx blocks and, for increased
      reliability, after a MAC soft reset.
      
      Impelement a complete MAC soft reset and reconfig procedure
      following the latest HW advisories - gfar_mac_reset() - to
      replace gfar_mac_init() and (the confusing) init_registers()
      functions.
      
      Factor out separate config functions for RCTRL and TCTRL,
      insure programming order of the relevant config regs after
      MAC soft reset.
      
      Split gfar_hw_init() into gfar_mac_reset() and the remaining
      global regs that don't need to be reconfigured after MAC soft
      reset (FIFOCFG, ATTRELI, HW counters a.s.o).
      
      As gfar_hw_init() now makes all the register writes @probe()
      time, based on all the device flags and config options, it
      must be moved further down, just before register_netdev(),
      as the last config step when the config values are comitted
      to HW.  Also, move netif_carrier_off() after register_netdev(),
      because it has no effect if called before.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      a328ac92
  15. 21 2月, 2014 1 次提交
  16. 19 2月, 2014 7 次提交
    • R
      NET: fec: only enable napi if we are successful · ce5eaf02
      Russell King 提交于
      If napi is left enabled after a failed attempt to bring the interface
      up, we BUG:
      
      fec 2188000.ethernet eth0: no PHY, assuming direct connection to switch
      libphy: PHY fixed-0:00 not found
      fec 2188000.ethernet eth0: could not attach to PHY
      ------------[ cut here ]------------
      kernel BUG at include/linux/netdevice.h:502!
      Internal error: Oops - BUG: 0 [#1] SMP ARM
      ...
      PC is at fec_enet_open+0x4d0/0x500
      LR is at __dev_open+0xa4/0xfc
      
      Only enable napi after we are past all the failure paths.
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ce5eaf02
    • C
      gianfar: Remove clean_rx_ring race from gfar_ethtool · 7cca336a
      Claudiu Manoil 提交于
      gfar_clean_rx_ring() was designed to be called from napi
      (rx softirq) context to do the Rx processing. Calling it
      from a process context like this is a bug as it will
      clearly race with the napi Rx processing.
      
      There's also no point in initializing num_txbdfree since
      startup_gfar() already does that, when bringing the device
      up again (after reset). Changing num_txbdfree "on-the-fly"
      like this is also subject to race conditions.  num_txbdfree
      is handled by the Tx processing path and the device reset
      procedure.  Also, don't assume that num_rx_queues is always
      equal to num_tx_queues.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      7cca336a
    • C
      gianfar: Add missing graceful reset steps and fixes · c10650b6
      Claudiu Manoil 提交于
      gfar_halt() and gfar_start() are responsible for stopping
      and starting the DMA and the Rx/Tx hw rings. They implement
      the support for the "graceful Rx/Tx stop/start" hw procedure,
      and also disable/enable eTSEC's hw interrupts in the process.
      
      The GRS/GTS procedure requires however to have the RQUEUE/TQUEUE
      registers cleared first and to wait for a period of time for the
      current frame to pass through the interface (around ~10ms for a
      jumbo frame). Only then may the GTS and GRS bits from DMACTRL be
      set to shut down the DMA, and finally the Tx_EN and Rx_EN bits in
      MACCFG1 may be cleared to disable the Tx/Rx blocks.
      
      The same register programming order applies to start the Rx/Tx:
      enabling the RQUEUE/TQUEUE *before* clearing the GRS/GTS bits.
      
      This is a HW recommendation in order to avoid a possible
      controller "lock up" during graceful reset.
      
      Cleanup the gfar_halt()/start() prototypes, to take priv instead
      of ndev as their purpose is to operate on HW. Enabling the
      RQUEUE/TQUEUE in the hw_init() is not needed anymore since
      that's the job of gfar_start().
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      c10650b6
    • C
      gianfar: Factor out enabling/disabling of hw interrupts · efeddce7
      Claudiu Manoil 提交于
      Throughout the code there are places where the controller's
      hw interrupt sources need to get disabled/enabled (masked/
      un-masked) all at once.  The recommendation for disabling
      the interrupts is to clear the ievent first then the imask
      register (not the other way around).
      Use the gfar_ints_enable/disable() helpers to make these
      operations consistent.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      efeddce7
    • C
      gianfar: Remove useless HAS_PADDING device flag · 532c37bc
      Claudiu Manoil 提交于
      The RCTRL updates of the FSL_GIANFAR_DEV_HAS_PADDING device
      flag get overriden by the FSL_GIANFAR_DEV_HAS_TIMER flag
      settings, which impose a Rx padding alignment of 8 bytes.
      As all the eTSEC devices that set HAS_PADDING also set the
      HAS_TIMER flag, the HAS_PADDING flag is now obsolete.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      532c37bc
    • C
      gianfar: Remove sysfs stubs for FIFOCFG and stashing · 34018fd4
      Claudiu Manoil 提交于
      Removing the sysfs stubs for the Tx FIFOCFG and ATTRELI
      (stashing) config registers, as these registers may only
      be configured after a MAC reset, with the controller stopped
      (i.e. during hw init, at probe() time).  The current sysfs
      stubs allow on-the-fly updates of these registers (the locking
      measures are useless and only add unecessary code).
      
      Changing these registers is discouraged. Only the default values
      will be used instead.
      
      Moreover, the stashing (ATTRELI) configuration options were
      effectively disabled (didn't get to the hw anyway if changed)
      because the stashing device_flags (HAS_BD_STASHING|HAS_BUF_STASHING)
      were "accidentally" cleared during probe().
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      34018fd4
    • C
      gianfar: Cleanup/Fix gfar_probe and the hw init code · 20862788
      Claudiu Manoil 提交于
      Factor out gfar_hw_init() to contain all the controller hw
      initialization steps for a better control of register writes,
      and to significantly simplify the tangled code from gfar_probe().
      This results in code size and stack usage reduction (besides
      code readability).
      
      Fix memory leak on device removal, by freeing the rx_/tx_queue
      structures.
      
      Replace custom bit swapping function with a library one (bitrev8).
      
      Move allocation of rx_/tx_queue struct arrays before the group
      structure init, because in order to assign Rx/Tx queues
      to groups we need to have the queues first.  This also allows
      earlier bail out of gfar_probe(), in case the memory allocation
      fails.
      
      The flow control checks for maccfg1 were removed from gfar_probe(),
      since flow control is disabled at probe time (priv->rx_/tx_pause_en
      are 0). Redundant initializations (by 0) also removed.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      20862788
  17. 17 1月, 2014 1 次提交
  18. 16 1月, 2014 1 次提交
    • C
      gianfar: Fix portabilty issues for ethtool and ptp · 42851e88
      Claudiu Manoil 提交于
      Fixes unhandled register write in gianfar_ethtool.c.
      Fixes following endianess related functional issues,
      reported by sparse as well, i.e.:
      
      gianfar_ethtool.c:1058:33: warning:
          incorrect type in argument 1 (different base types)
          expected unsigned int [unsigned] [usertype] value
          got restricted __be32 [usertype] ip4src
      
      gianfar_ethtool.c:1164:33: warning:
          restricted __be16 degrades to integer
      
      gianfar_ethtool.c:1669:32: warning:
          invalid assignment: ^=
          left side has type restricted __be16
          right side has type int
      
      Solves all the sparse warnings for mixig normal pointers
      with __iomem pointers for gianfar_ptp.c, i.e.:
      gianfar_ptp.c:163:32: warning:
          incorrect type in argument 1 (different address spaces)
          expected unsigned int [noderef] <asn:2>*addr
          got unsigned int *<noident>
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      42851e88
  19. 06 1月, 2014 1 次提交
  20. 30 12月, 2013 1 次提交
  21. 27 12月, 2013 1 次提交
  22. 20 12月, 2013 1 次提交
  23. 12 12月, 2013 1 次提交
  24. 03 12月, 2013 1 次提交
    • S
      net: fec_main: dma_map() only the length of the skb · 2488a54e
      Sebastian Siewior 提交于
      On tx submit the driver always dma_map_single() FEC_ENET_TX_FRSIZE (=2048)
      bytes. This works because we don't overwrite any memory after the data buffer,
      we remove it from cache if it was there. So we hurt performace in case the
      mapping of a smaller area makes a difference.
      There is also a bug: If the data area starts shortly before the end of
      RAM say 0xc7fffa10 and the RAM ends at 0xc8000000 then we have enough
      space to fit the data area (according to skb->len) but we would map beyond
      end of ram if we are using 2048. In v2.6.31 (against which kernel this patch
      made) there is the following check in dma_cache_maint():
      
      |BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1));
      
      Since the area starting at 0xc8000000 is no longer virt_addr_valid() we
      BUG() during dma_map_single(). The BUG() statement was removed in v3.5-rc1 as
      per 2dc6a016 ("ARM: dma-mapping: use asm-generic/dma-mapping-common.h").
      
      This patch was tested on v2.6.31 and then forward-ported and compile
      tested only against the net tree. I think it is still worth fixing
      mainline even after the BUG() statement is gone.
      Tested-by: NFugang Duan <B38611@freescale.com>
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
      Acked-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2488a54e
  25. 22 11月, 2013 2 次提交
  26. 15 11月, 2013 1 次提交
    • D
      net:fec: fix WARNING caused by lack of calls to dma_mapping_error() · d842a31f
      Duan Fugang-B38611 提交于
      The driver fails to check the results of DMA mapping and results in
      the following warning: (with kernel config "CONFIG_DMA_API_DEBUG" enable)
      
      ------------[ cut here ]------------
      WARNING: at lib/dma-debug.c:937 check_unmap+0x43c/0x7d8()
      fec 2188000.ethernet: DMA-API: device driver failed to check map
      error[device address=0x00000000383a8040] [size=2048 bytes] [mapped as single]
      
      Modules linked in:
      CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.17-16827-g9cdb0ba-dirty #188
      [<80013c4c>] (unwind_backtrace+0x0/0xf8) from [<80011704>] (show_stack+0x10/0x14)
      [<80011704>] (show_stack+0x10/0x14) from [<80025614>] (warn_slowpath_common+0x4c/0x6c)
      [<80025614>] (warn_slowpath_common+0x4c/0x6c) from [<800256c8>] (warn_slowpath_fmt+0x30/0x40)
      [<800256c8>] (warn_slowpath_fmt+0x30/0x40) from [<8026bfdc>] (check_unmap+0x43c/0x7d8)
      [<8026bfdc>] (check_unmap+0x43c/0x7d8) from [<8026c584>] (debug_dma_unmap_page+0x6c/0x78)
      [<8026c584>] (debug_dma_unmap_page+0x6c/0x78) from [<8038049c>] (fec_enet_rx_napi+0x254/0x8a8)
      [<8038049c>] (fec_enet_rx_napi+0x254/0x8a8) from [<804dc8c0>] (net_rx_action+0x94/0x160)
      [<804dc8c0>] (net_rx_action+0x94/0x160) from [<8002c758>] (__do_softirq+0xe8/0x1d0)
      [<8002c758>] (__do_softirq+0xe8/0x1d0) from [<8002c8e8>] (do_softirq+0x4c/0x58)
      [<8002c8e8>] (do_softirq+0x4c/0x58) from [<8002cb50>] (irq_exit+0x90/0xc8)
      [<8002cb50>] (irq_exit+0x90/0xc8) from [<8000ea88>] (handle_IRQ+0x3c/0x94)
      [<8000ea88>] (handle_IRQ+0x3c/0x94) from [<8000855c>] (gic_handle_irq+0x28/0x5c)
      [<8000855c>] (gic_handle_irq+0x28/0x5c) from [<8000de00>] (__irq_svc+0x40/0x50)
      Exception stack(0x815a5f38 to 0x815a5f80)
      5f20:                                                       815a5f80 3b9aca00
      5f40: 0fe52383 00000002 0dd8950e 00000002 81e7b080 00000000 00000000 815ac4d8
      5f60: 806032ec 00000000 00000017 815a5f80 80059028 8041fc4c 60000013 ffffffff
      [<8000de00>] (__irq_svc+0x40/0x50) from [<8041fc4c>] (cpuidle_enter_state+0x50/0xf0)
      [<8041fc4c>] (cpuidle_enter_state+0x50/0xf0) from [<8041fd94>] (cpuidle_idle_call+0xa8/0x14c)
      [<8041fd94>] (cpuidle_idle_call+0xa8/0x14c) from [<8000edac>] (arch_cpu_idle+0x10/0x4c)
      [<8000edac>] (arch_cpu_idle+0x10/0x4c) from [<800582f8>] (cpu_startup_entry+0x60/0x130)
      [<800582f8>] (cpu_startup_entry+0x60/0x130) from [<80bc7a48>] (start_kernel+0x2d0/0x328)
      [<80bc7a48>] (start_kernel+0x2d0/0x328) from [<10008074>] (0x10008074)
      ---[ end trace c6edec32436e0042 ]---
      
      Because dma-debug add new interfaces to debug dma mapping errors, pls refer
      to: http://lwn.net/Articles/516640/
      
      After dma mapping, it must call dma_mapping_error() to check mapping error,
      otherwise the map_err_type alway is MAP_ERR_NOT_CHECKED, check_unmap() define
      the mapping is not checked and dump the error msg. So,add dma_mapping_error()
      checking to fix the WARNING
      
      And RX DMA buffers are used repeatedly and the driver copies it into an skb,
      fec_enet_rx() should not map or unmap, use dma_sync_single_for_cpu()/dma_sync_single_for_device()
      instead of dma_map_single()/dma_unmap_single().
      
      There have another potential issue:  fec_enet_rx() passes the DMA address to __va().
      Physical and DMA addresses are *not* the same thing. They may differ if the device
      is behind an IOMMU or bounce buffering was required, or just because there is a fixed
      offset between the device and host physical addresses. Also fix it in this patch.
      
      =============================================
      V2: add net_ratelimit() to limit map err message.
          use dma_sync_single_for_cpu() instead of dma_map_single().
          fix the issue that pass DMA addresses to __va() to get virture address.
      V1: initial send
      =============================================
      Signed-off-by: NFugang Duan <B38611@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      d842a31f