Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP eMMC PHY.
Access the PHY via registers provided by GRF (general register
files) module.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The HiSilicon Hi6220 USB PHY is available in HiSilicon Hi6220 SoCs only.
Restrict it to HiSilicon arm64, unless compile-testing.
Signed-off-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The BCM7xxx ARM-based and MIPS-based platforms share a similar hardware
block for AHCI SATA3.

This new compatible string, "brcm,bcm7425-sata-phy", may be used for
most MIPS-based platforms of 40nm process technology.
Signed-off-by: NJaedon Shin <jaedon.shin@gmail.com>
Acked-by: NRob Herring <robh@kernel.org>
Tested-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Support hi6220 use phy for HiKey board
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds support for R-Car generation 3 USB2 PHY driver.
This SoC has 3 EHCI/OHCI channels, and the channel 0 is shared
with the HSUSB (USB2.0 peripheral) device. And each channel has
independent registers about the PHYs.

So, the purpose of this driver is:
 1) initializes some registers of SoC specific to use the
    {ehci,ohci}-platform driver.

 2) detects id pin to select host or peripheral on the channel 0.

For now, this driver only supports 1) above.
Signed-off-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The sun9i usb phy driver calls of_usb_get_phy_mode(), which is not
available if USB is disabled:

drivers/built-in.o: In function `sun9i_usb_phy_probe':
:(.text+0x7fb0): undefined reference to `of_usb_get_phy_mode'

This adds a dependency to avoid the randconfig build errors.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 9c3b4430 ("phy: Add driver to support individual USB PHYs on sun9i")
Acked-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch adds the PCIe PHY support for the Broadcom PCIe RC interface
on Cygnus
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NArun Parameswaran <aparames@broadcom.com>
Reviewed-by: NJD (Jiandong) Zheng <jdzheng@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

support usb3.0 phy of mt65xx SoCs
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

On some boards there is no vbus_det gpio pin, instead vbus-detection for
otg can be done via the pmic.

This commit adds support for monitoring vbus_det via the power_supply
exported by the pmic, enabling support for otg on these boards.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The sunxi musb glue needs to know if a host or normal usb cable is plugged
in, add extcon support so that the musb glue can monitor the host status.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NChanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add PHY driver for the internal USB OTG PHY found on NXP
LPC18xx and LPC43xx devices. This driver takes care of
enabling the PHY in CREG (syscon) and setting the required
clock frequency.
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Fix this compile error:

drivers/built-in.o: In function 'mv_usb2_phy_probe':
phy-pxa-28nm-usb2.c:(.text+0x25ec): undefined reference to
'devm_ioremap_resource'
drivers/built-in.o: In function 'mv_hsic_phy_probe':
phy-pxa-28nm-hsic.c:(.text+0x3084): undefined reference to
'devm_ioremap_resource'
Signed-off-by: NSebastian Ott <sebott@linux.vnet.ibm.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a driver for the USB2.0 PHY found on the IMG Pistachio SoC.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hartley <james.hartley@imgtec.com>
Cc: Damien Horsley <Damien.Horsley@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9728/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add PHY driver for the Marvell HSIC 28nm PHY. This PHY is found in PXA1928
SOC.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Add driver for USB 28nm PHY found in Marvell PXA1928 SOC.
Signed-off-by: NRob Herring <robh@kernel.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Supports up to two ports which can each be powered on/off and configured
independently.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

TUSB1210 ULPI PHY has vendor specific register for eye
diagram tuning. On some platforms the system firmware has
set optimized value to it. In order to not loose the
optimized value, the driver stores it during probe and
restores it every time the PHY is powered back on.
Signed-off-by: NHeikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: NDavid Cohen <david.a.cohen@linux.intel.com>
Acked-by: NKishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>

DM816x PHY uses usb_phy_* methods and because
of that, it must select USB_PHY, however, because
the drivers in question (DM816x, TWL4030 and
OMAP_USB2) sit outside of drivers/usb/ directory,
meaning they can be built even if USB_SUPPORT=n.

This patches fixes the dependencies by adding
USB_SUPPORT as a dependency and making all drivers
select USB_PHY (which cannot be selected through
menuconfig).

Note that this fixes some linking breakages when
building with randconfig.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This phy only exists on platforms under ARCH_QCOM, not ARCH_MSM.

Cc: Yaniv Gardi <ygardi@codeaurora.org>
Cc: Dov Levenglick <dovl@codeaurora.org>
Cc: Christoph Hellwig <hch@lst.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NYaniv Gardi <ygardi@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.

This adds a new driver to support the regular USB PHYs.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a minimal driver for dm816x USB. This makes USB work on dm816x
without any other changes needed as it can use the existing musb_dsps
glue layer for the USB controller.

Note that this phy is different from dm814x and am335x.

Cc: Bin Liu <binmlist@gmail.com>
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Paul Bolle <pebolle@tiscali.nl>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.
Signed-off-by: NYunzhi Li <lyz@rock-chips.com>
Tested-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This change adds a generic and common API support for ufs phy QUALCOMM
Technologies. This support provides common code and also points
to specific phy callbacks to differentiate between different behaviors
of frequent use-cases (like power on, power off, phy calibration etc).
Signed-off-by: NYaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: NDov Levenglick <dovl@codeaurora.org>
Signed-off-by: NChristoph Hellwig <hch@lst.de>

The Armada 375 SoC comes with an USB2 host and device controller and
an USB3 controller. The USB cluster control register allows to manage
common features of both USB controllers.

This commit adds a driver integrated in the generic PHY framework to
control this USB cluster feature.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
[ kishon@ti.com : Made it to use the updated devm_phy_create API and
		  soem cosmentic changes in Kconfig file.]
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>
Acked-by: NJason Cooper <jason@lakedaemon.net>

This PHY controller is also present on Exynos7 platform
in arch-exynos family.
So PHY_EXYNOS5_USBDRD should now depend on ARCH_EXYNOS.
Signed-off-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add the driver driving the Marvell Berlin USB PHY. This allows to
initialize the PHY and to use it from the USB driver later.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The MiPHY28lp is a Generic PHY which can serve various SATA or PCIe
or USB3 devices.
Signed-off-by: Nalexandre torgue <alexandre.torgue@st.com>
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This driver adds support for USB (1.1 and 2.0) phy for STiH415 and
STiH416 System-On-Chips from STMicroelectronics.
Signed-off-by: NMaxime Coquelin <maxime.coquelin@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This is the generic phy driver for the picoPHY ports used by the
USB2 and USB3 Host controllers when controlling usb2/1.1 devices. It
is found on STiH407 SoC family from STMicroelectronics.
Signed-off-by: NGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

This PHY, though formally being a part of Renesas USBHS controller, contains the
UGCTRL2 register that controls multiplexing of the USB ports (Renesas calls them
channels) to the different USB controllers: channel 0 can be connected to either
PCI EHCI/OHCI or USBHS controllers, channel 2 can be connected to PCI EHCI/OHCI
or xHCI controllers.

This is a new driver for this USB PHY currently already supported under drivers/
usb/phy/. The reason for writing the new driver was the requirement that the
multiplexing  of USB channels to the controller be dynamic, depending on what
USB drivers  are loaded,  rather than static as provided by the old driver. The
infrastructure provided by drivers/phy/phy-core.c  seems to fit that purpose
ideally. The new driver only  supports device tree probing  for now.
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

ST SPEAR1340-MIPHY support should be available only on
ST SPEAr1340 machine.
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

ST SPEAR1310-MIPHY support should be available only on
ST SPEAr1310 machine.
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Enabling GENERIC_PHY in the shared (by most ARM sub-architectures)
defconfig multi_v7_defconfig is prohibited.  Instead, we'll enable
it from the Kconfig whenever PHY_MIPHY365X is enabled.

Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
IPQ806x family of SoCs.
Signed-off-by: NKumar Gala <galak@codeaurora.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

The Berlin SoC has a two SATA ports. Add a PHY driver to handle them.

The mode selection can let us think this PHY can be configured to fit
other purposes. But there are reasons to think the SATA mode will be
the only one usable: the PHY registers are only accessible indirectly
through two registers in the SATA range, the PHY seems to be integrated
and no information tells us the contrary. For these reasons, make the
driver a SATA PHY driver.
Signed-off-by: NAntoine Ténart <antoine.tenart@free-electrons.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
Depend on MACH_KIRKWOOD, which will be set when these SoCs are built
as part of mach-mvebv.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

Add a PHY driver for uses with AHCI based SATA controller driver on the
APQ8064 family of SoCs.

This patch is a forward port from Qualcomm's v3.4 andriod kernel.

Tested on IFC6410 board.

CC: Sujit Reddy Thumma <sthumma@codeaurora.org>
Tested-by: NKiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>

USB DWC3 driver on Exynos platform does not work without its
corresponding phy driver. Hence make the PHY driver depend on
Exynos DWC3 driver and default it to yes to make things easier
for the end user.
Signed-off-by: NSachin Kamat <sachin.kamat@samsung.com>
Reviewed-by: NJingoo Han <jg1.han@samsung.com>
Tested-by: NVivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: NKishon Vijay Abraham I <kishon@ti.com>