The unsafe doorbell and scratchpad access should display reason when
WARN is called.  Otherwise we get a stack dump without any explanation.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Printouts driver name and version to indicate what is being loaded.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Instead of using the platform code names, use the correct platform names
to identify the respective Intel NTB hardware.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Allocate memory for the NUMA node of the NTB device.
Signed-off-by: NAllen Hubbe <Allen.Hubbe@emc.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Add module parameters for the addresses to be used in B2B topology.
Signed-off-by: NAllen Hubbe <Allen.Hubbe@emc.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Set errata flags for the specific device IDs to which they apply,
instead of the whole Xeon hardware class.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Link training should be enabled in the driver probe for root port mode.
We should not have to wait for transport to be loaded for this to
happen.  Otherwise the ntb device will not show up on the transparent
bridge side of the link.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Change ntb_hw_intel to use the new NTB hardware abstraction layer.

Split ntb_transport into its own driver.  Change it to use the new NTB
hardware abstraction layer.
Signed-off-by: NAllen Hubbe <Allen.Hubbe@emc.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

This patch only moves files to their new locations, before applying the
next two patches adding the NTB Abstraction layer.  Splitting this patch
from the next is intended make distinct which code is changed only due
to moving the files, versus which are substantial code changes in adding
the NTB Abstraction layer.
Signed-off-by: NAllen Hubbe <Allen.Hubbe@emc.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Commit ab760a0c (ntb: Adding split BAR support for Haswell platforms)
changed ntb_device's mw from a fixed-size array into a pointer that is
allocated based on limits.max_mw; however, on Atom platforms, max_mw
is not initialized until ntb_device_setup(), which happens after the
allocation.

Fill out max_mw in ntb_atom_detect() to match ntb_xeon_detect(); this
happens before the use of max_mw in the ndev->mw allocation.

Fixes a null pointer dereference on Atom platforms with ntb hardware.

v2: fix typo (mw_max should be max_mw)
Signed-off-by: NDaniel Verkamp <daniel.verkamp@intel.com>
Acked-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

The MW regbase and vbase(s) were not being freed if an error occurred
in the vbase allocation loop.  This is corrected by updating the error
path for the allocation loop to err4.
Reported-by: NJulia Lawall <julia.lawall@lip6.fr>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

The PCI core now disables MSI and MSI-X for all devices during enumeration
regardless of CONFIG_PCI_MSI.  Remove device-specific code to disable
MSI/MSI-X.
Signed-off-by: NMichael S. Tsirkin <mst@redhat.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>

On the Haswell platform, a split BAR option to allow creation of 2
32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this
new option.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Instead of using a module parameter, we should detect the errata via
PCI DID and then set an appropriate flag. This will be used for additional
errata later on.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

To simplify some of the platform detection code. Move the platform detection
to a function to be called earlier.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Move the platform detection function to separate functions to allow
easier maintenence.
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NJon Mason <jdmason@kudzu.us>

Create a debugfs entry for the NTB device to log the basic device info,
as well as display the error count on a number of registers.
Signed-off-by: NJon Mason <jon.mason@intel.com>

As result of deprecation of MSI-X/MSI enablement functions
pci_enable_msix() and pci_enable_msi_block() all drivers
using these two interfaces need to be updated to use the
new pci_enable_msi_range()  or pci_enable_msi_exact()
and pci_enable_msix_range() or pci_enable_msix_exact()
interfaces.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

This is an cleanup effort to make ntb_setup_msix() more
readable - use ntb_setup_bwd_msix() to init MSI-Xs on
BWD hardware and ntb_setup_snb_msix() - on SNB hardware.

Function ntb_setup_snb_msix() also initializes MSI-Xs the
way it should has been done - looping pci_enable_msix()
until success or failure.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

Some white space and 80 char overruns corrected.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

In the code for Xeon devices in back-to-back mode with xeon_errata_workaround
disabled, the downstream device puts the wrong value in SNB_B2B_XLAT_OFFSETL
(SNB_MBAR01_DSD_ADDR vs. SNB_MBAR01_USD_ADDR).

This was spotted while reading code, since the typo has no practical effect,
at least for now: the low 32 bits of both constants are actually identical
anyway.  However, it's clearer and safer to use the right name.
Signed-off-by: NRoland Dreier <roland@purestorage.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

Disable interrupts and poll under high load
Signed-off-by: NJon Mason <jon.mason@intel.com>

Enable Snoop from Primary to Secondary side on BAR23 and BAR45 on all
TLPs.  Previously, Snoop was only enabled from Secondary to Primary
side.  This can have a performance improvement on some workloads.

Also, make the code more obvious about how the link is being enabled.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Add a comment describing the necessary ordering of modifications to the
NTB Limit and Base registers.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Current MSI-X enablement code assumes MSI-Xs were successfully
allocated in case less than requested vectors were available.
That assumption is wrong, since MSI-Xs should be enabled with
a repeated call to pci_enable_msix(). This update fixes this.
Signed-off-by: NAlexander Gordeev <agordeev@redhat.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

The Xeon NTB-RP setup, the transparent side does not get a link up/down
interrupt.  Since the presence of a NTB device on the transparent side
means that we have a NTB link up, we can work around the lack of an
interrupt by simply calling the link up function to notify the upper
layers.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Modifications to the 14th bit of the B2BDOORBELL register will not be
mirrored to the remote system due to a hardware issue.  To get around
the issue, shrink the number of available doorbell bits by 1.  The max
number of doorbells was being used as a way to referencing the Link
Doorbell bit.  Since this would no longer work, the driver must now
explicitly reference that bit.

This does not affect the xeon_errata_workaround case, as it is not using
the b2bdoorbell register.
Signed-off-by: NJon Mason <jon.mason@intel.com>

PCI core will initialize device MSI/MSI-X capability in
pci_msi_init_pci_dev(). So device driver should use
pci_dev->msi_cap/msix_cap to determine whether the device
support MSI/MSI-X instead of using
pci_find_capability(pci_dev, PCI_CAP_ID_MSI/MSIX).
Access to PCIe device config space again will consume more time.
Signed-off-by: NYijing Wang <wangyijing@huawei.com>
Signed-off-by: NJon Mason <jon.mason@intel.com>

Update NTB version to 1.0
Signed-off-by: NJon Mason <jon.mason@intel.com>

Add "data" ntb_register_db_callback parameter description comment and
correct poor spelling.
Signed-off-by: NJon Mason <jon.mason@intel.com>

NTB-RP is not a supported configuration on BWD hardware.  Remove the
code attempting to set it up.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Add support for Non-Transparent Bridge connected to a PCI-E Root Port on
the remote system (also known as NTB-RP mode).  This allows for a NTB
enabled system to be connected to a non-NTB enabled system/slot.

Modifications to the registers and BARs/MWs on the Secondary side by the
remote system are reflected into registers on the Primary side for the
local system.  Similarly, modifications of registers and BARs/MWs on
Primary side by the local system are reflected into registers on the
Secondary side for the Remote System.  This allows communication between
the 2 sides via these registers and BARs/MWs.

Note: there is not a fix for the Xeon Errata (that was already worked
around in NTB-B2B mode) for NTB-RP mode.  Due to this limitation, NTB-RP
will not work on the Secondary side with the Xeon Errata workaround
enabled.  To get around this, disable the workaround via the
xeon_errata_workaround=0 modparm.  However, this can cause the hang
described in the errata.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Many variable names in the NTB driver refer to the primary or secondary
side.  However, these variables will be used to access the reverse case
when in NTB-RP mode.  Make these names more generic in anticipation of
NTB-RP support.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Allocate and use a DMA engine channel to transmit and receive data over
NTB.  If none is allocated, fall back to using the CPU to transfer data.
Signed-off-by: NJon Mason <jon.mason@intel.com>
Reviewed-by: NDan Williams <dan.j.williams@intel.com>
Reviewed-by: NDave Jiang <dave.jiang@intel.com>

Correct the issues on NTB that prevented it from working on x86_32 and
modify the Kconfig to allow it to be permitted to be used in that
environment as well.
Signed-off-by: NJon Mason <jon.mason@intel.com>

Add support for new Intel NTB devices on upcoming Xeon hardware.  Since
the Xeon hardware design is already in place in the driver, all that is
needed are the new device ids.

Remove the device IDs for NTB devs running in Transparent Bridge mode,
as this driver is not being used for those devices.

Rename the device IDs for NTB devs running in NTB-RP mode to better
identify their usage model.  "PS" to denote the Primary Side of NTB, and
"SS" to denote the secondary side.  The primary side is the interface
exposed to the local system, and the secondary side is the interface
exposed to the remote system.
Signed-off-by: NJon Mason <jon.mason@intel.com>

The BWD NTB device will drop the link if an error is encountered on the
point-to-point PCI bridge.  The link will stay down until all errors are
cleared and the link is re-established.  On link down, check to see if
the error is detected, if so do the necessary housekeeping to try and
recover from the error and reestablish the link.

There is a potential race between the 2 NTB devices recovering at the
same time.  If the times are synchronized, the link will not recover and the
driver will be stuck in this loop forever.  Add a random interval to the
recovery time to prevent this race.
Signed-off-by: NJon Mason <jon.mason@intel.com>

There is a Xeon hardware errata related to writes to SDOORBELL or
B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, which
may hang the system.  To workaround this issue, use one of the memory
windows to access the interrupt and scratch pad registers on the remote
system.  This bypasses the issue, but removes one of the memory windows
from use by the transport.  This reduction of MWs necessitates adding
some logic to determine the number of available MWs.

Since some NTB usage methodologies may have unidirectional traffic, the
ability to disable the workaround via modparm has been added.

See BF113 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-c5500-c3500-spec-update.pdf
See BT119 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdfSigned-off-by: NJon Mason <jon.mason@intel.com>