[ Upstream commit c432a29d3fc9ee928caeca2f5cf68b3aebfa6817 ]

isp iommu requires wrapper variants of the clocks.
noc variants are always on and using the wrapper variants will activate
{A,H}CLK_ISP{0,1} due to the hierarchy.

Tested using the pending isp patch set (which is not upstream
yet). Without this patch, streaming from the isp stalls.

Also add the respective power domain and remove the "disabled" status.

Refer:
 RK3399 TRM v1.4 Fig. 2-4 RK3399 Clock Architecture Diagram
 RK3399 TRM v1.4 Fig. 8-1 RK3399 Power Domain Partition
Signed-off-by: NHelen Koike <helen.koike@collabora.com>
Tested-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NSasha Levin <sashal@kernel.org>

commit a3eec13b8fd2b9791a21fa16e38dfea8111579bf upstream.

When using direct commands (DCMDs) on an RK3399, we get spurious
CQE completion interrupts for the DCMD transaction slot (#31):

[  931.196520] ------------[ cut here ]------------
[  931.201702] mmc1: cqhci: spurious TCN for tag 31
[  931.206906] WARNING: CPU: 0 PID: 1433 at /usr/src/kernel/drivers/mmc/host/cqhci.c:725 cqhci_irq+0x2e4/0x490
[  931.206909] Modules linked in:
[  931.206918] CPU: 0 PID: 1433 Comm: irq/29-mmc1 Not tainted 4.19.8-rt6-funkadelic #1
[  931.206920] Hardware name: Theobroma Systems RK3399-Q7 SoM (DT)
[  931.206924] pstate: 40000005 (nZcv daif -PAN -UAO)
[  931.206927] pc : cqhci_irq+0x2e4/0x490
[  931.206931] lr : cqhci_irq+0x2e4/0x490
[  931.206933] sp : ffff00000e54bc80
[  931.206934] x29: ffff00000e54bc80 x28: 0000000000000000
[  931.206939] x27: 0000000000000001 x26: ffff000008f217e8
[  931.206944] x25: ffff8000f02ef030 x24: ffff0000091417b0
[  931.206948] x23: ffff0000090aa000 x22: ffff8000f008b000
[  931.206953] x21: 0000000000000002 x20: 000000000000001f
[  931.206957] x19: ffff8000f02ef018 x18: ffffffffffffffff
[  931.206961] x17: 0000000000000000 x16: 0000000000000000
[  931.206966] x15: ffff0000090aa6c8 x14: 0720072007200720
[  931.206970] x13: 0720072007200720 x12: 0720072007200720
[  931.206975] x11: 0720072007200720 x10: 0720072007200720
[  931.206980] x9 : 0720072007200720 x8 : 0720072007200720
[  931.206984] x7 : 0720073107330720 x6 : 00000000000005a0
[  931.206988] x5 : ffff00000860d4b0 x4 : 0000000000000000
[  931.206993] x3 : 0000000000000001 x2 : 0000000000000001
[  931.206997] x1 : 1bde3a91b0d4d900 x0 : 0000000000000000
[  931.207001] Call trace:
[  931.207005]  cqhci_irq+0x2e4/0x490
[  931.207009]  sdhci_arasan_cqhci_irq+0x5c/0x90
[  931.207013]  sdhci_irq+0x98/0x930
[  931.207019]  irq_forced_thread_fn+0x2c/0xa0
[  931.207023]  irq_thread+0x114/0x1c0
[  931.207027]  kthread+0x128/0x130
[  931.207032]  ret_from_fork+0x10/0x20
[  931.207035] ---[ end trace 0000000000000002 ]---

The driver shows this message only for the first spurious interrupt
by using WARN_ONCE(). Changing this to WARN() shows, that this is
happening quite frequently (up to once a second).

Since the eMMC 5.1 specification, where CQE and CQHCI are specified,
does not mention that spurious TCN interrupts for DCMDs can be simply
ignored, we must assume that using this feature is not working reliably.

The current implementation uses DCMD for REQ_OP_FLUSH only, and
I could not see any performance/power impact when disabling
this optional feature for RK3399.

Therefore this patch disables DCMDs for RK3399.
Signed-off-by: NChristoph Muellner <christoph.muellner@theobroma-systems.com>
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixes: 84362d79 ("mmc: sdhci-of-arasan: Add CQHCI support for arasan,sdhci-5.1")
Cc: stable@vger.kernel.org
[the corresponding code changes are queued for 5.2 so doing that as well]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Commit 0fbc47d9 ("phy: rockchip-typec: deprecate some DT properties
for various register fields.") deprecates some Rockchip Type-C
properties. As these are now not needed, remove from the device tree
file.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Those pins would be used by many boards.
Signed-off-by: NRandy Li <ayaka@soulik.info>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The soc spdif and i2s controllers always only have one compontent, so
always require #sound-dai-cells to be 0. Therefore there is no need to
duplicate this property in individual boards.

So move them to rk3399.dtsi.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The cooling device properties, like "#cooling-cells" and
"dynamic-power-coefficient", should either be present for all the CPUs
of a cluster or none. If these are present only for a subset of CPUs of
a cluster then things will start falling apart as soon as the CPUs are
brought online in a different order. For example, this will happen
because the operating system looks for such properties in the CPU node
it is trying to bring up, so that it can register a cooling device.

Add such missing properties.

Do minor rearrangement as well to keep ordering consistent.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Everything is in place and working, it only needed to be wired up.
Signed-off-by: NVicente Bergas <vicencb@gmail.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Update all 64bit rockchip devicetree files to use SPDX-License-Identifiers.

All devicetrees claim to be either GPL or X11 while the actual license
text is MIT. Therefore we use MIT for the SPDX tag as X11 is clearly
wrong.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Acked-by: NBrian Norris <briannorris@chromium.org>
Acked-by: NMatthias Brugger <mbrugger@suse.com>
Acked-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add clocks in iommu nodes, since we are going to control clocks in
rockchip iommu driver.
Signed-off-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the usb3 phyter for the USB3.0 OTG controller.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

These clocks do not assign default clock frequency, and use the
default cru register value to get frequency, so if cpll increase
frequency, these clocks also increase their frequency, that may
exceed their signed off frequency. So assign default clock for
them to avoid it.

NOTE: on none of the boards currently in mainline do we expect
CPLL to be anything other than 800 MHz, but some future boards
might have it. It's still good to be explicit about the clock
rates to make diffing against future boards easier and also to
rely less on BIOS muxing.
Signed-off-by: NLin Huang <hl@rock-chips.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The ACLK_VIO is a parent clock used by a several children,
its suggested clock rate is 400MHz. Right now it gets 400MHz
because it sources from CPLL(800M) and divides by 2 after reset.
It's good not to rely on default values like this, so let's
explicitly set it.
NOTE: it's expected that at least one board may override cru node and
set the CPLL to 1.6 GHz. On that board it will be very important to be
explicit about aclk-vio being 400 MHz.
Signed-off-by: NShunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This reverts commit c301b327.

While this works splendidly on rk3399-gru devices using the cros-ec
extcon, other rk3399-based devices using the fusb302 or no power-delivery
controller at all don't probe at all anymore, as the typec-phy currently
always expects the extcon to be available and therefore defers probing
indefinitly on these.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add a node for the cdn DP controller which is embedded in the rk3399
SoC.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
[fixed whitespaces instead of tabs, dropped unnecessary address+size-cells
 and fixed the number of interrupt cells]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add pin definition for I2S0 if used as a 2-channel only bus.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

There are three pins can act as cif test clock for rk3399.
They're sourced from 24M and output 24M by default and some boards
may use them as camera 24M xvclk.
Signed-off-by: NShunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The pclk_vio_grf supply power for VIO GRF IOs, if it is disabled,
driver would failed to operate the VIO GRF registers.

The clock is optional but one of the side effects of don't have this clk
is that the Samsung Chromebook Plus fails to recover display after a
suspend/resume with following errors:

    rockchip-dp ff970000.edp: Input stream clock not detected.
    rockchip-dp ff970000.edp: Timeout of video streamclk ok
    rockchip-dp ff970000.edp: unable to config video
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
[this should also fix display failures when building rockchip-drm as module]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the usb3 phyter for the USB3.0 OTG controller.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

After commit '06c47e62 usb: dwc3: of-simple: Add support to get resets
for the device' you can add the reset property to the dwc3 node, the reset
is required for the controller to work properly, otherwise bind / unbind
stress testing of the USB controller on rk3399 we'd often end up with lots
of failures that looked like this:

  phy phy-ff800000.phy.9: phy poweron failed --> -110
  dwc3 fe900000.dwc3: failed to initialize core
  dwc3: probe of fe900000.dwc3 failed with error -110
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The aclk_usb3 must be enabled to support USB3 for rk3399.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the usb3 power-domain, its qos area and assign it to the usb device
node.
Signed-off-by: NEnric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We might include additional ports in derivative device trees, so the
'port' node should have an address, and the parent 'ports' node needs
/#{addres,size}-cells.
Signed-off-by: NNickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch adds the information for the secondary MIPI DSI controller,
e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing
definition for dsi0.
Signed-off-by: NNickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We've documented this one already, but we didn't add it to the DTSI yet.
Suggested-by: NNickey Yang <nickey.yang@rock-chips.com>
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch add the RGA dt config of RK3399 SoC.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add the HDMI CEC controller main clock coming from the CRU.
Signed-off-by: NPierre-Hugues Husson <phh@phh.me>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The clk of grf must be enabled before writing grf
register for rk3399.
Signed-off-by: NNickey Yang <nickey.yang@rock-chips.com>
[the grf clock is already part of the binding since march 2017]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

There is a further gate in between the mipidphy reference clock and the
actual ref-clock input to the dsi host, making the clock hirarchy look like
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll

Fix the clock reference so that the whole clock subtree gets enabled when
the dsi host needs it.
Signed-off-by: NNickey Yang <nickey.yang@rock-chips.com>
[amended commit message]
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Convert all RK3399 platforms to use per-lane PHY model in order to save
more power by idling unused lane(s).
Tested-by: NJeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: NBrian Norris <briannorris@chromium.org>

Add VPU/VDEC/IEP/ISP0/ISP1 iommu nodes
Signed-off-by: NSimon Xue <xxm@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

We need to init vop aclk and hclk incase the U-Boot does not do
the initialize.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Reviewed-by: NMark Yao <mark.yao@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

RK3399 USB DWC3 controller has a issue that FS/LS devices not
recognized if inserted through USB 3.0 HUB. It's because that
the inter-packet delay between the SSPLIT token to SETUP token
is about 566ns, more then the USB spec requirement.

This patch adds a quirk "snps,dis-tx-ipgap-linecheck-quirk" to
disable the u2mac linestate check to decrease the SSPLIT token
to SETUP token inter-packet delay from 566ns to 466ns.
Signed-off-by: NWilliam Wu <william.wu@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an hdmi node, and also add hdmi endpoints to vopb and vopl
output port nodes.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an mipi node, and also add mipi endpoints to vopb and vopl
output port nodes.
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add an edp node, and also add edp endpoints to vopb and vopl
output port nodes.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

1. add pd node for RK3399 Soc
2. create power domain tree
3. add qos node for domain
Signed-off-by: NElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add devicetree nodes for rk3399 VOP (Video Output Processors), and the
top level display-subsystem root node.

Later patches add endpoints (eDP, HDMI, MIPI, etc) that attach to the
VOPs' output ports.
Signed-off-by: NMark Yao <mark.yao@rock-chips.com>
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NJacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This patch updates the dynamic-power-coefficient for big cluster on
rk3399 SoCs.

The dynamic power consumption of the CPU is proportional to the square of
the Voltage (V) and the clock frequency (f). The coefficient is used to
calculate the dynamic power as below -
Pdyn = dynamic-power-coefficient * V^2 * f
Where Voltage is in uV, frequency is in MHz.

As the following is the tested data on rk3399's big cluster.
frequency(MHz)  Voltage(V)  Current(mA) Dynamic-power-coefficient
24              0.8         15
48              0.8         23          ~417
96              0.8         40          ~443
216             0.8         82          ~438
312             0.8         115         ~430
408             0.8         150         ~455
So the dynamic-power-coefficient average value is about 436.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Kill these two pinctrl reference totally from rk3399 as it
never work indeed.
Signed-off-by: NShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

Add Mali GPU device tree node for the RK3399 SoCs, with devfreq
opp table.

RK3399 and RK3399-OP1 SoCs have a different recommendation table with
gpu opp. Also, the ARM's mali driver found on
https://developer.arm.com/products/software/mali-drivers/midgard-kernel.
Signed-off-by: NCaesar Wang <wxt@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>