1. 17 7月, 2010 1 次提交
    • B
      PCI: fall back to original BIOS BAR addresses · 58c84eda
      Bjorn Helgaas 提交于
      If we fail to assign resources to a PCI BAR, this patch makes us try the
      original address from BIOS rather than leaving it disabled.
      
      Linux tries to make sure all PCI device BARs are inside the upstream
      PCI host bridge or P2P bridge apertures, reassigning BARs if necessary.
      Windows does similar reassignment.
      
      Before this patch, if we could not move a BAR into an aperture, we left
      the resource unassigned, i.e., at address zero.  Windows leaves such BARs
      at the original BIOS addresses, and this patch makes Linux do the same.
      
      This is a bit ugly because we disable the resource long before we try to
      reassign it, so we have to keep track of the BIOS BAR address somewhere.
      For lack of a better place, I put it in the struct pci_dev.
      
      I think it would be cleaner to attempt the assignment immediately when the
      claim fails, so we could easily remember the original address.  But we
      currently claim motherboard resources in the middle, after attempting to
      claim PCI resources and before assigning new PCI resources, and changing
      that is a fairly big job.
      
      Addresses https://bugzilla.kernel.org/show_bug.cgi?id=16263Reported-by: NAndrew <nitr0@seti.kr.ua>
      Tested-by: NAndrew <nitr0@seti.kr.ua>
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      58c84eda
  2. 20 5月, 2010 1 次提交
  3. 10 5月, 2010 1 次提交
    • M
      i7core_edac: Add a code to probe Xeon 55xx bus · d1fd4fb6
      Mauro Carvalho Chehab 提交于
      This code changes the detection procedure of i7core_edac. Instead of
      directly probing for MC registers, it probes for another register found
      on Nehalem. If found, it tries to pick the first MC PCI BUS. This should
      work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255
      that are not properly detected by the non-legacy PCI methods.
      
      The new detection code scans specifically at buses 254 and 255 for the
      Xeon 55xx devices.
      
      This code has not tested yet. After working, a change at the code will
      be needed, since the i7core is not yet ready for working with 2 sets of
      MC.
      Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
      d1fd4fb6
  4. 10 4月, 2010 1 次提交
  5. 13 3月, 2010 2 次提交
  6. 28 2月, 2010 5 次提交
  7. 24 2月, 2010 2 次提交
    • B
      PCI: augment bus resource table with a list · 2fe2abf8
      Bjorn Helgaas 提交于
      Previously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources
      forwarded to a bus by its upstream bridge.  We've increased this size
      several times when the table overflowed.
      
      But there's no good limit on the number of resources because host bridges
      and subtractive decode bridges can forward any number of ranges to their
      secondary buses.
      
      This patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries,
      which corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4)
      bridge can positively decode.  Any additional resources, e.g., PCI host
      bridge windows or subtractively-decoded regions, are kept in a list.
      
      I'd prefer a single list rather than this split table/list approach, but
      that requires simultaneous changes to every architecture.  This approach
      only requires immediate changes where we set up (a) host bridges with more
      than four windows and (b) subtractive-decode P2P bridges, and we can
      incrementally change other architectures to use the list.
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      2fe2abf8
    • B
      PCI: add pci_bus_for_each_resource(), remove direct bus->resource[] refs · 89a74ecc
      Bjorn Helgaas 提交于
      No functional change; this converts loops that iterate from 0 to
      PCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the
      pci_bus_for_each_resource() iterator instead.
      
      This doesn't change the way resources are stored; it merely removes
      dependencies on the fact that they're in a table.
      Signed-off-by: NBjorn Helgaas <bjorn.helgaas@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      89a74ecc
  8. 23 2月, 2010 13 次提交
  9. 20 2月, 2010 1 次提交
  10. 13 2月, 2010 1 次提交
  11. 06 2月, 2010 1 次提交
  12. 29 1月, 2010 1 次提交
  13. 05 1月, 2010 1 次提交
    • R
      PCI/PM: Use per-device D3 delays · 1ae861e6
      Rafael J. Wysocki 提交于
      It turns out that some PCI devices require extra delays when changing
      power state from D3 to D0 (and the other way around).  Although this
      is against the PCI specification, we can handle it quite easily by
      allowing drivers to define arbitrary D3 delays for devices known to
      require extra time for switching power states.
      
      Introduce additional field d3_delay in struct pci_dev and use it to
      store the value of the device's D0->D3 delay, in miliseconds.  Make
      the PCI PM core code use the per-device d3_delay unless
      pci_pm_d3_delay is greater (in which case the latter is used).
      [This also allows the driver to specify d3_delay shorter than the
       10 ms required by the PCI standard if the device is known to be able
       to handle that.]
      
      Make the sky2 driver set d3_delay to 150 for devices handled by it.
      
      Fixes http://bugzilla.kernel.org/show_bug.cgi?id=14730 which is a
      listed regression from 2.6.30.
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      1ae861e6
  14. 17 12月, 2009 1 次提交
    • B
      PCI/cardbus: Add a fixup hook and fix powerpc · 2d1c8618
      Benjamin Herrenschmidt 提交于
      The cardbus code creates PCI devices without ever going through the
      necessary fixup bits and pieces that normal PCI devices go through.
      
      There's in fact a commented out call to pcibios_fixup_bus() in there,
      it's commented because ... it doesn't work.
      
      I could make pcibios_fixup_bus() do the right thing on powerpc easily
      but I felt it cleaner instead to provide a specific hook pci_fixup_cardbus
      for which a weak empty implementation is provided by the PCI core.
      
      This fixes cardbus on powerbooks and probably all other PowerPC
      platforms which was broken completely for ever on some platforms and
      since 2.6.31 on others such as PowerBooks when we made the DMA ops
      mandatory (since those are setup by the fixups).
      Acked-by: NDominik Brodowski <linux@dominikbrodowski.net>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      2d1c8618
  15. 15 12月, 2009 1 次提交
    • D
      PCI: Global variable decls must match the defs in section attributes · 491424c0
      David Howells 提交于
      Global variable declarations must match the definitions in section attributes
      as the compiler is at liberty to vary the method it uses to access a variable,
      depending on the section it is in.
      
      When building the FRV arch, I now see:
      
        drivers/built-in.o: In function `pci_apply_final_quirks':
        drivers/pci/quirks.c:2606: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
        drivers/pci/quirks.c:2623: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
        drivers/pci/quirks.c:2630: relocation truncated to fit: R_FRV_GPREL12 against symbol `pci_dfl_cache_line_size' defined in .devinit.data section in drivers/built-in.o
      
      because the declaration of pci_dfl_cache_line_size in linux/pci.h does not
      match the definition in drivers/pci/pci.c.
      Signed-off-by: NDavid Howells <dhowells@redhat.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      491424c0
  16. 05 12月, 2009 1 次提交
    • C
      PCI: add pci_request_acs · 5d990b62
      Chris Wright 提交于
      Commit ae21ee65 "PCI: acs p2p upsteram
      forwarding enabling" doesn't actually enable ACS.
      
      Add a function to pci core to allow an IOMMU to request that ACS
      be enabled.  The existing mechanism of using iommu_found() in the pci
      core to know when ACS should be enabled doesn't actually work due to
      initialization order;  iommu has only been detected not initialized.
      
      Have Intel and AMD IOMMUs request ACS, and Xen does as well during early
      init of dom0.
      
      Cc: Allen Kay <allen.m.kay@intel.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Jeremy Fitzhardinge <jeremy@goop.org>
      Cc: Joerg Roedel <joerg.roedel@amd.com>
      Signed-off-by: NChris Wright <chrisw@sous-sol.org>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      5d990b62
  17. 25 11月, 2009 2 次提交
  18. 07 11月, 2009 1 次提交
  19. 05 11月, 2009 3 次提交
    • A
      PCI: add pci_get_domain_bus_and_slot function · 3c299dc2
      Andrew Patterson 提交于
      Added the pci_get_domain_and_slot_function which is analogous to
      pci_get_bus_and_slot. It returns a pci_dev given a domain (segment) number,
      bus number, and devnr. Like pci_get_bus_and_slot,
      pci_get_domain_bus_and_slot holds a reference to the returned pci_dev.
      
      Converted pci_get_bus_and_slot to a wrapper that calls
      pci_get_domain_bus_and_slot with the domain hard-coded to 0.
      
      This routine was patterned off code suggested by Bjorn Helgaas.
      Acked-by: NHuang Ying <ying.huang@intel.com>
      Signed-off-by: NAndrew Patterson <andrew.patterson@hp.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      3c299dc2
    • M
      PCI: PCIe AER: honor ACPI HEST FIRMWARE FIRST mode · 05843961
      Matt Domsch 提交于
      Feedback from Hidetoshi Seto and Kenji Kaneshige incorporated.  This
      correctly handles PCI-X bridges, PCIe root ports and endpoints, and
      prints debug messages when invalid/reserved types are found in the
      HEST.  PCI devices not in domain/segment 0 are not represented in
      HEST, thus will be ignored.
      
      Today, the PCIe Advanced Error Reporting (AER) driver attaches itself
      to every PCIe root port for which BIOS reports it should, via ACPI
      _OSC.
      
      However, _OSC alone is insufficient for newer BIOSes.  Part of ACPI
      4.0 is the new APEI (ACPI Platform Error Interfaces) which is a way
      for OS and BIOS to handshake over which errors for which components
      each will handle.  One table in ACPI 4.0 is the Hardware Error Source
      Table (HEST), where BIOS can define that errors for certain PCIe
      devices (or all devices), should be handled by BIOS ("Firmware First
      mode"), rather than be handled by the OS.
      
      Dell PowerEdge 11G server BIOS defines Firmware First mode in HEST, so
      that it may manage such errors, log them to the System Event Log, and
      possibly take other actions.  The aer driver should honor this, and
      not attach itself to devices noted as such.
      
      Furthermore, Kenji Kaneshige reminded us to disallow changing the AER
      registers when respecting Firmware First mode.  Platform firmware is
      expected to manage these, and if changes to them are allowed, it could
      break that firmware's behavior.
      
      The HEST parsing code may be replaced in the future by a more
      feature-rich implementation.  This patch provides the minimum needed
      to prevent breakage until that implementation is available.
      Reviewed-by: NKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Reviewed-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      Signed-off-by: NMatt Domsch <Matt_Domsch@dell.com>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      05843961
    • T
      pccard: configure CLS on attach · 15ea76d4
      Tejun Heo 提交于
      For non hotplug PCI devices, the system firmware usually configures
      CLS correctly.  For pccard devices system firmware can't do it and
      Linux PCI layer doesn't do it either.  Unfortunately this leads to
      poor performance for certain devices (sata_sil).  Unless MWI, which
      requires separate configuration, is to be used, CLS doesn't affect
      correctness, so the configuration should be harmless.
      
      This patch makes pci_set_cacheline_size() always built and export it
      and make pccard call it during attach.
      
      Please note that some other PCI hotplug drivers (shpchp and pciehp)
      also configure CLS on hotplug.
      Signed-off-by: NTejun Heo <tj@kernel.org>
      Cc: Daniel Ritz <daniel.ritz@gmx.ch>
      Cc: Dominik Brodowski <linux@dominikbrodowski.net>
      Cc: Greg KH <greg@kroah.com>
      Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
      Cc: Axel Birndt <towerlexa@gmx.de>
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      15ea76d4