- 10 3月, 2015 6 次提交
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由 Aaro Koskinen 提交于
Add OCTEON SHA512 module. Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Aaro Koskinen 提交于
Add OCTEON SHA256 module. Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Aaro Koskinen 提交于
Add OCTEON SHA1 module. Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Aaro Koskinen 提交于
Add instruction definitions for SHA1/256/512. Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Aaro Koskinen 提交于
Always disable preemption on behalf of the drivers when crypto engine is taken into use. This will simplify the usage. Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Aaro Koskinen 提交于
Don't disable bottom half while the crypto engine is in use, as it should be unnecessary: All kernel crypto engine usage is wrapped with crypto engine state save/restore, so if we get interrupted by softirq that uses crypto they should save and restore our context. This actually fixes an issue when running OCTEON MD5 with interrupts disabled (tcrypt mode=302). There's a WARNING because the module is trying to enable the bottom half with irqs disabled: [ 52.656610] ------------[ cut here ]------------ [ 52.661439] WARNING: CPU: 1 PID: 428 at /home/aaro/git/linux/kernel/softirq.c:150 __local_bh_enable_ip+0x9c/0xd8() [ 52.671780] Modules linked in: tcrypt(+) [...] [ 52.763539] [<ffffffff8114082c>] warn_slowpath_common+0x94/0xd8 [ 52.769465] [<ffffffff81144614>] __local_bh_enable_ip+0x9c/0xd8 [ 52.775390] [<ffffffff81119574>] octeon_md5_final+0x12c/0x1e8 [ 52.781144] [<ffffffff81337050>] shash_compat_digest+0xd0/0x1b0 Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 09 3月, 2015 1 次提交
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由 Kim Phillips 提交于
The current cryptodev-2.6 tree commits: d9850fc5 ("crypto: powerpc/sha1 - kernel config") 50ba29aa ("crypto: powerpc/sha1 - glue") failed to properly place files under arch/powerpc/crypto, which leads to build errors: make[1]: *** No rule to make target 'arch/powerpc/crypto/sha1-spe-asm.o', needed by 'arch/powerpc/crypto/sha1-ppc-spe.o'. Stop. make[1]: *** No rule to make target 'arch/powerpc/crypto/sha1_spe_glue.o', needed by 'arch/powerpc/crypto/sha1-ppc-spe.o'. Stop. Makefile:947: recipe for target 'arch/powerpc/crypto' failed Move the two sha1 spe files under crypto/, and whilst there, rename other powerpc crypto files with underscores to use dashes for consistency. Cc: Markus Stockhausen <stockhausen@collogia.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 04 3月, 2015 3 次提交
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由 Markus Stockhausen 提交于
Integrate the module into the kernel config tree. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Glue code for crypto infrastructure. Call the assembler code where required. Take a little care about small input data. Kick out early for input chunks < 64 bytes and replace memset for context cleanup with simple loop. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
This is the assembler code for the MD5 implementation. Handling of algorithm constants has been slightly changed to reduce register usage and make better use of cores with multiple ALUs. Thus they are stored as delta values. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 02 3月, 2015 3 次提交
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由 Markus Stockhausen 提交于
Integrate the module into the kernel config tree. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Glue code for crypto infrastructure. Call the assembler code where required. Disable preemption during calculation and enable SPE instructions in the kernel prior to the call. Avoid to disable preemption for too long. Take a little care about small input data. Kick out early for input chunks < 64 bytes and replace memset for context cleanup with simple loop. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
This is the assembler code for SHA1 implementation with the SIMD SPE instruction set. With the enhanced instruction set we can operate on 2 32 bit words in parallel. That helps reducing the time to calculate W16-W79. For increasing performance even more the assembler function can compute hashes for more than one 64 byte input block. The state of the used SPE registers is preserved via the stack so we can run from interrupt context. There might be the case that we interrupt ourselves and push sensitive data from another context onto our stack. Clear this area in the stack afterwards to avoid information leakage. The code is endian independant. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 01 3月, 2015 8 次提交
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由 Markus Stockhausen 提交于
Integrate the module into the kernel configuration Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Integrate the assembler modules into the kernel crypto framework. Take care to avoid long intervals of disabled preemption. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
The assembler block cipher module that controls the core AES functions. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Key generation for big endian core routines. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
The assembler AES encryption and decryption core routines. Implemented & optimized for big endian. Nevertheless they work on little endian too. For most efficient reuse in (higher level) block cipher routines they are implemented as "fast" call modules without any stack handling or register saving. The caller must take care of that part. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
4K AES tables for big endian. To reduce the possiblity of timing attacks, the size has been cut to 8KB + 256 bytes in contrast to 16KB in the generic implementation. That is not perfect but at least a good tradeoff for CPU limited router devices. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Define some register aliases for better readability. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Florian Fainelli 提交于
Now that these definitions have been moved to drivers/char/hw_random/bcm63xx-rng.c where they belong to make the driver standalone, we can safely remove these definitions from bcm63xx_regs.h. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 28 2月, 2015 1 次提交
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由 Tadeusz Struk 提交于
Changed the __driver-gcm-aes-aesni to be a proper aead algorithm. This required a valid setkey and setauthsize functions to be added and also some changes to make sure that math context is not corrupted when the alg is used directly. Note that the __driver-gcm-aes-aesni should not be used directly by modules that can use it in interrupt context as we don't have a good fallback mechanism in this case. Signed-off-by: NAdrian Hoban <adrian.hoban@intel.com> Signed-off-by: NTadeusz Struk <tadeusz.struk@intel.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 27 2月, 2015 4 次提交
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由 Lad, Prabhakar 提交于
this patch fixes following sparse warning: sha1_mb_mgr_init_avx2.c:59:31: warning: constant 0xF76543210 is so big it is long Signed-off-by: NLad, Prabhakar <prabhakar.csengg@gmail.com> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Integrate the module into the kernel config tree. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
Glue code for crypto infrastructure. Call the assembler code where required. Disable preemption during calculation and enable SPE instructions in the kernel prior to the call. Avoid to disable preemption for too long. Take a little care about small input data. Kick out early for input chunks < 64 bytes and replace memset for context cleanup with simple loop. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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由 Markus Stockhausen 提交于
This is the assembler code for SHA256 implementation with the SIMD SPE instruction set. Although being only a 32 bit architecture GPRs are extended to 64 bit presenting two 32 bit values. With the enhanced instruction set we can operate on them in parallel. That helps reducing the time to calculate W16-W64. For increasing performance even more the assembler function can compute hashes for more than one 64 byte input block. That saves a lot of register saving/restoring The state of the used SPE registers is preserved via the stack so we can run from interrupt context. There might be the case that we interrupt ourselves and push sensitive data from another context onto our stack. Clear this area in the stack afterwards to avoid information leakage. The code is endian independant. Signed-off-by: NMarkus Stockhausen <stockhausen@collogia.de> Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>
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- 23 2月, 2015 1 次提交
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由 David Howells 提交于
Convert the following where appropriate: (1) S_ISLNK(dentry->d_inode) to d_is_symlink(dentry). (2) S_ISREG(dentry->d_inode) to d_is_reg(dentry). (3) S_ISDIR(dentry->d_inode) to d_is_dir(dentry). This is actually more complicated than it appears as some calls should be converted to d_can_lookup() instead. The difference is whether the directory in question is a real dir with a ->lookup op or whether it's a fake dir with a ->d_automount op. In some circumstances, we can subsume checks for dentry->d_inode not being NULL into this, provided we the code isn't in a filesystem that expects d_inode to be NULL if the dirent really *is* negative (ie. if we're going to use d_inode() rather than d_backing_inode() to get the inode pointer). Note that the dentry type field may be set to something other than DCACHE_MISS_TYPE when d_inode is NULL in the case of unionmount, where the VFS manages the fall-through from a negative dentry to a lower layer. In such a case, the dentry type of the negative union dentry is set to the same as the type of the lower dentry. However, if you know d_inode is not NULL at the call site, then you can use the d_is_xxx() functions even in a filesystem. There is one further complication: a 0,0 chardev dentry may be labelled DCACHE_WHITEOUT_TYPE rather than DCACHE_SPECIAL_TYPE. Strictly, this was intended for special directory entry types that don't have attached inodes. The following perl+coccinelle script was used: use strict; my @callers; open($fd, 'git grep -l \'S_IS[A-Z].*->d_inode\' |') || die "Can't grep for S_ISDIR and co. callers"; @callers = <$fd>; close($fd); unless (@callers) { print "No matches\n"; exit(0); } my @cocci = ( '@@', 'expression E;', '@@', '', '- S_ISLNK(E->d_inode->i_mode)', '+ d_is_symlink(E)', '', '@@', 'expression E;', '@@', '', '- S_ISDIR(E->d_inode->i_mode)', '+ d_is_dir(E)', '', '@@', 'expression E;', '@@', '', '- S_ISREG(E->d_inode->i_mode)', '+ d_is_reg(E)' ); my $coccifile = "tmp.sp.cocci"; open($fd, ">$coccifile") || die $coccifile; print($fd "$_\n") || die $coccifile foreach (@cocci); close($fd); foreach my $file (@callers) { chomp $file; print "Processing ", $file, "\n"; system("spatch", "--sp-file", $coccifile, $file, "--in-place", "--no-show-diff") == 0 || die "spatch failed"; } [AV: overlayfs parts skipped] Signed-off-by: NDavid Howells <dhowells@redhat.com> Signed-off-by: NAl Viro <viro@zeniv.linux.org.uk>
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- 21 2月, 2015 2 次提交
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由 Niklas Cassel 提交于
Commit e9de688d ("irqchip: mips-gic: Support local interrupts") updated several platforms. This is a copy paste error. Signed-off-by: NNiklas Cassel <niklass@axis.com> Reviewed-by: NAndrew Bresticker <abrestic@chromium.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9245/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Andreas Ruprecht 提交于
In commit c441d4a5 ("MIPS: mm: Only build one microassembler that is suitable"), the Makefile at arch/mips/mm was rewritten to only build the "right" microassembler file, depending on whether CONFIG_CPU_MICROMIPS is set or not. In the files, however, there are still preprocessor definitions depending on CONFIG_CPU_MICROMIPS. The #ifdef around them can now never evaluate to true, so let's remove them altogether. This inconsistency was found using the undertaker-checkpatch tool. Signed-off-by: NAndreas Ruprecht <rupran@einserver.de> Reviewed-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Valentin Rothberg <valentinrothberg@gmail.com> Cc: Paul Bolle <pebolle@tiscali.nl> Patchwork: https://patchwork.linux-mips.org/patch/9267/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 20 2月, 2015 11 次提交
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由 David Daney 提交于
- Use of_irq_init() to initialize interrupt controllers - Get rid of some unlikely() - Add CIB to support SATA and other interrupts - Add support for CIU SUM2 interrupt sources Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NLeonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: NPeter Swain <peter.swain@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8947/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
The acknowledge bits don't exist for level triggered irqs, so setting them causes the simulator to terminate. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NLeonid Rosenboim <lrosenboim@caviumnetworks.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8946/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chandrakala Chavva 提交于
Read clock rate from the correct CSR. Don't clear COP0_DCACHE for OCTEONIII. Signed-off-by: NChandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8945/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chad Reese 提交于
CN38XX pass 1 required icache prefetching to be turned off. This chip never reached production and is long dead. Other processor specific icache settings are done by the bootloader. Remove these bits from the kernel. Signed-off-by: NChad Reese <kreese@caviumnetworks.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8944/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8943/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Add coverage for OCTEON III models. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8942/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Make messages refer to all CN6XXX. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8941/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Also update union octeon_cvmemctl with new OCTEON II fields. [aleksey.makarov@auriga.com: use __BITFIELD_FIELD] Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8940/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David Daney 提交于
Disable ICache prefetch for certian Octeon II processors. Signed-off-by: NDavid Daney <david.daney@cavium.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8938/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Aleksey Makarov 提交于
Commit 2c952e06 ("MIPS: Move cop2 save/restore to switch_to()") removes assembler code to store COP2 registers. Commit a36d8225 ("MIPS: OCTEON: Enable use of FPU") mistakenly restores it Fixes: a36d8225 ("MIPS: OCTEON: Enable use of FPU") Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8937/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chandrakala Chavva 提交于
Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register, its a 64-bit wide. Signed-off-by: NChandrakala Chavva <cchavva@caviumnetworks.com> Signed-off-by: NAleksey Makarov <aleksey.makarov@auriga.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: David Daney <david.daney@cavium.com> Patchwork: https://patchwork.linux-mips.org/patch/8936/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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