1. 27 10月, 2010 1 次提交
  2. 26 10月, 2010 1 次提交
  3. 12 10月, 2010 1 次提交
  4. 05 10月, 2010 1 次提交
    • P
      sh: intc: Support virtual mappings for IRQ subgroups. · c1e30ad9
      Paul Mundt 提交于
      Many interrupts that share a single mask source but are on different
      hardware vectors will have an associated register tied to an INTEVT that
      denotes the precise cause for the interrupt exception being triggered.
      
      This introduces the concept of IRQ subgroups in the intc core, where
      a virtual IRQ map is constructed for each of the pre-defined cause bits,
      and a higher level chained handler takes control of the parent INTEVT.
      This enables CPUs with heavily muxed IRQ vectors (especially across
      disjoint blocks) to break things out in to a series of managed chained
      handlers while being able to dynamically lookup and adopt the IRQs
      created for them.
      
      This is largely an opt-in interface, requiring CPUs to manually submit
      IRQs for subgroup splitting, in addition to providing identifiers in
      their enum maps that can be used for lazy lookup via the radix tree.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      c1e30ad9
  5. 26 4月, 2010 1 次提交
  6. 15 4月, 2010 1 次提交
    • P
      sh: intc: IRQ auto-distribution support. · dc825b17
      Paul Mundt 提交于
      This implements support for hardware-managed IRQ balancing as implemented
      by SH-X3 cores (presently only hooked up for SH7786, but can probably be
      carried over to other SH-X3 cores, too).
      
      CPUs need to specify their distribution register along with the mask
      definitions, as these follow the same format. Peripheral IRQs that don't
      opt out of balancing will be automatically distributed at the whim of the
      hardware block, while each CPU needs to verify whether it is handling the
      IRQ or not, especially before clearing the mask.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      dc825b17
  7. 15 12月, 2009 1 次提交
  8. 02 11月, 2009 1 次提交
    • P
      sh: intc: Handle legacy IRQ reservation in vector map. · 45b9deaf
      Paul Mundt 提交于
      Different CPUs will have different starting vectors, with varying
      amounts of reserved or unusable vector space prior to the first slot.
      This introduces a legacy vector reservation system that inserts itself in
      between the CPU vector map registration and the platform specific IRQ
      setup. This works fine in practice as the only new vectors that boards
      need to establish on their own should be dynamically allocated rather
      than arbitrarily assigned. As a plus, this also makes all of the
      converted platforms sparseirq ready.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      45b9deaf
  9. 26 10月, 2009 1 次提交
    • P
      sh: __irq_entry annotate do_IRQ(). · ba93483f
      Paul Mundt 提交于
      This adds an __irq_entry annotation for do_IRQ() so that the IRQ
      annotation in the function graph tracer works as advertized. We already
      have the IRQENTRY section wired up, so this is just a trivial addition
      to actually make use of it.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ba93483f
  10. 14 10月, 2009 1 次提交
  11. 21 9月, 2009 1 次提交
  12. 01 9月, 2009 1 次提交
    • P
      sh: nmi_debug support. · 1e1030dc
      Paul Mundt 提交于
      This implements support for NMI debugging that was shamelessly copied
      from the avr32 port. A bit of special magic is needed in the interrupt
      exception path given that the NMI exception handler is stubbed in to the
      regular exception handling table despite being reported in INTEVT. So we
      mangle the lookup and kick off an EXPEVT-style exception dispatch from
      the INTEVT path for exceptions that do_IRQ() has no chance of handling.
      As a result, we also drop the evt2irq() conversion from the do_IRQ() path
      and just do it in assembly.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      1e1030dc
  13. 24 8月, 2009 1 次提交
  14. 17 8月, 2009 1 次提交
  15. 14 8月, 2009 1 次提交
  16. 11 7月, 2009 1 次提交
    • P
      sh: Replace DEBUG_STACKOVERFLOW with STACK_DEBUG. · 9f14b84a
      Paul Mundt 提交于
      STACK_DEBUG ties in to mcount in order to do function-granular stack
      overflow checks as opposed to lazily checking from IRQ context. As the
      default is nohz, the frequency of overflow checking is too irregular to
      catch much useful information, and so the mcount approach employed by
      sparc64 is adopted instead.
      
      This kills off the old check entirely from the do_IRQ() path and now
      adopts CONFIG_MCOUNT instead.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      9f14b84a
  17. 22 5月, 2009 2 次提交
  18. 27 2月, 2009 1 次提交
    • M
      sh: multiple vectors per irq - base · bdaa6e80
      Magnus Damm 提交于
      Instead of keeping the single vector -> single linux irq mapping
      we extend the intc code to support merging of vectors to a single
      linux irq. This helps processors such as sh7750, sh7780 and sh7785
      which have more vectors than masking ability. With this patch in
      place we can modify the intc tables to use one irq per maskable
      irq source. Please note the following:
      
       - If multiple vectors share the same enum then only the
         first vector will be available as a linux irq.
      
       - Drivers may need to be rewritten to get pending irq
         source from the hardware block instead of irq number.
      
      This patch together with the sh7785 specific intc tables solves
      DMA controller irq issues related to buggy interrupt masking.
      Reported-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
      Signed-off-by: NMagnus Damm <damm@igel.co.jp>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      bdaa6e80
  19. 11 1月, 2009 1 次提交
    • Y
      sparseirq: use kstat_irqs_cpu instead · dee4102a
      Yinghai Lu 提交于
      Impact: build fix
      
      Ingo Molnar wrote:
      
      > tip/arch/blackfin/kernel/irqchip.c: In function 'show_interrupts':
      > tip/arch/blackfin/kernel/irqchip.c:85: error: 'struct kernel_stat' has no member named 'irqs'
      > make[2]: *** [arch/blackfin/kernel/irqchip.o] Error 1
      > make[2]: *** Waiting for unfinished jobs....
      >
      
      So could move kstat_irqs array to irq_desc struct.
      
      (s390, m68k, sparc) are not touched yet, because they don't support genirq
      Signed-off-by: NYinghai Lu <yinghai@kernel.org>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      dee4102a
  20. 29 7月, 2008 1 次提交
  21. 29 4月, 2008 1 次提交
  22. 14 2月, 2008 1 次提交
  23. 07 11月, 2007 1 次提交
  24. 02 11月, 2007 1 次提交
    • P
      sh: Decouple 4k and soft/hardirq stacks. · 110ed282
      Paul Mundt 提交于
      While using separate IRQ stacks can cut down on stack consumption,
      many users can also use 4k stacks directly without the additional
      need of separate stacks for soft and hardirqs.
      
      With this split, we support the same rationale for 4KSTACKS as
      m68knommu, with the IRQSTACKS abstraction as per ppc64.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      110ed282
  25. 11 10月, 2007 1 次提交
  26. 20 7月, 2007 1 次提交
  27. 12 7月, 2007 1 次提交
  28. 07 5月, 2007 1 次提交
    • P
      sh: NR_IRQS consolidation. · be782df5
      Paul Mundt 提交于
      Each board sets the total number of IRQs that it's interested in via
      the machvec. Previously we cared about the off vs on-chip IRQ range,
      but any code relying on that is long dead. Set NR_IRQS to something
      sensible given the vector range, and allow boards to cap it if they
      really care.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      be782df5
  29. 14 3月, 2007 1 次提交
  30. 06 12月, 2006 3 次提交
    • J
      sh: sh775x/titan fixes for irq header changes. · ea0f8fea
      Jamie Lenehan 提交于
      The following moves the creation of IPR interupts into setup-7750.c
      and updates a few other things to make it all work after the "Drop
      CPU subtype IRQ headers" commit. It boots and runs fine on my titan
      board.
      
       - adds an ipr_idx to the ipr_data and uses a function in the subtype
         code to calculate the address of the IPR registers
      
       - adds a function to enable individual interrupt mode for externals
         in the subtype code and calls that from the titan board code
         instead of doing it directly.
      
       - I changed the shift in the ipr_data to be the actual # of bits to
         shift, instead of the numnber / 4 - made it easier to match with
         the manual.
      Signed-off-by: NJamie Lenehan <lenehan@twibble.org>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      ea0f8fea
    • P
      sh: Fixup 4K irq stacks. · 1dc41e58
      Paul Mundt 提交于
      There was a clobber issue with the register we were saving
      the stack in, so we switch to a register that we handle in
      the clobber list properly already.
      
      This also follows the x86 changes for allowing the softirq
      checks from hardirq context.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      1dc41e58
    • S
      sh: gcc4 support. · f0bc814c
      Stuart Menefy 提交于
      This fixes up the kernel for gcc4. The existing exception handlers
      needed some wrapping for pt_regs access, acessing the registers
      via a RELOC_HIDE() pointer.
      
      The strcpy() issues popped up here too, so add -ffreestanding and
      kill off the symbol export.
      Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      f0bc814c
  31. 19 10月, 2006 1 次提交
  32. 12 10月, 2006 1 次提交
    • P
      sh: interrupt exception handling rework · baf4326e
      Paul Mundt 提交于
      Kill off interrupt_table for all of the CPU subtypes, we now
      default in to stepping in to do_IRQ() for _all_ IRQ exceptions
      and counting the spurious ones, rather than simply flipping on
      the ones we cared about. This and enabling the IRQ by default
      automatically has already uncovered a couple of bugs and IRQs
      that weren't being caught, as well as some that are being
      generated far too often (SCI Tx Data Empty, for example).
      
      The general rationale is to use a marker for interrupt exceptions,
      test for it in the handle_exception() path, and skip out to
      do_IRQ() if it's found. Everything else follows the same behaviour
      of finding the cached EXPEVT value in r2/r2_bank, we just rip out
      the INTEVT read from entry.S entirely (except for in the kGDB NMI
      case, which is another matter).
      
      Note that while this changes the do_IRQ() semantics regarding r4
      handling, they were fundamentally broken anyways (relying entirely
      on r2_bank for the cached code). With this, we do the INTEVT read
      from do_IRQ() itself (in the CONFIG_CPU_HAS_INTEVT case), or fall
      back on r4 for the muxed IRQ number, which should also be closer
      to what SH-2 and SH-2A want anyways.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      baf4326e
  33. 06 10月, 2006 1 次提交
  34. 27 9月, 2006 2 次提交
  35. 30 6月, 2006 1 次提交
    • I
      [PATCH] genirq: rename desc->handler to desc->chip · d1bef4ed
      Ingo Molnar 提交于
      This patch-queue improves the generic IRQ layer to be truly generic, by adding
      various abstractions and features to it, without impacting existing
      functionality.
      
      While the queue can be best described as "fix and improve everything in the
      generic IRQ layer that we could think of", and thus it consists of many
      smaller features and lots of cleanups, the one feature that stands out most is
      the new 'irq chip' abstraction.
      
      The irq-chip abstraction is about describing and coding and IRQ controller
      driver by mapping its raw hardware capabilities [and quirks, if needed] in a
      straightforward way, without having to think about "IRQ flow"
      (level/edge/etc.) type of details.
      
      This stands in contrast with the current 'irq-type' model of genirq
      architectures, which 'mixes' raw hardware capabilities with 'flow' details.
      The patchset supports both types of irq controller designs at once, and
      converts i386 and x86_64 to the new irq-chip design.
      
      As a bonus side-effect of the irq-chip approach, chained interrupt controllers
      (master/slave PIC constructs, etc.) are now supported by design as well.
      
      The end result of this patchset intends to be simpler architecture-level code
      and more consolidation between architectures.
      
      We reused many bits of code and many concepts from Russell King's ARM IRQ
      layer, the merging of which was one of the motivations for this patchset.
      
      This patch:
      
      rename desc->handler to desc->chip.
      
      Originally i did not want to do this, because it's a big patch.  But having
      both "desc->handler", "desc->handle_irq" and "action->handler" caused a
      large degree of confusion and made the code appear alot less clean than it
      truly is.
      
      I have also attempted a dual approach as well by introducing a
      desc->chip alias - but that just wasnt robust enough and broke
      frequently.
      
      So lets get over with this quickly.  The conversion was done automatically
      via scripts and converts all the code in the kernel.
      
      This renaming patch is the first one amongst the patches, so that the
      remaining patches can stay flexible and can be merged and split up
      without having some big monolithic patch act as a merge barrier.
      
      [akpm@osdl.org: build fix]
      [akpm@osdl.org: another build fix]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      d1bef4ed
  36. 23 3月, 2006 1 次提交
    • A
      [PATCH] more for_each_cpu() conversions · 394e3902
      Andrew Morton 提交于
      When we stop allocating percpu memory for not-possible CPUs we must not touch
      the percpu data for not-possible CPUs at all.  The correct way of doing this
      is to test cpu_possible() or to use for_each_cpu().
      
      This patch is a kernel-wide sweep of all instances of NR_CPUS.  I found very
      few instances of this bug, if any.  But the patch converts lots of open-coded
      test to use the preferred helper macros.
      
      Cc: Mikael Starvik <starvik@axis.com>
      Cc: David Howells <dhowells@redhat.com>
      Acked-by: NKyle McMartin <kyle@parisc-linux.org>
      Cc: Anton Blanchard <anton@samba.org>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Cc: Paul Mundt <lethal@linux-sh.org>
      Cc: "David S. Miller" <davem@davemloft.net>
      Cc: William Lee Irwin III <wli@holomorphy.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: Christian Zankel <chris@zankel.net>
      Cc: Philippe Elie <phil.el@wanadoo.fr>
      Cc: Nathan Scott <nathans@sgi.com>
      Cc: Jens Axboe <axboe@suse.de>
      Cc: Eric Dumazet <dada1@cosmosbay.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      394e3902