1. 26 3月, 2010 3 次提交
    • P
      x86, perf, bts, mm: Delete the never used BTS-ptrace code · faa4602e
      Peter Zijlstra 提交于
      Support for the PMU's BTS features has been upstreamed in
      v2.6.32, but we still have the old and disabled ptrace-BTS,
      as Linus noticed it not so long ago.
      
      It's buggy: TIF_DEBUGCTLMSR is trampling all over that MSR without
      regard for other uses (perf) and doesn't provide the flexibility
      needed for perf either.
      
      Its users are ptrace-block-step and ptrace-bts, since ptrace-bts
      was never used and ptrace-block-step can be implemented using a
      much simpler approach.
      
      So axe all 3000 lines of it. That includes the *locked_memory*()
      APIs in mm/mlock.c as well.
      Reported-by: NLinus Torvalds <torvalds@linux-foundation.org>
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Roland McGrath <roland@redhat.com>
      Cc: Oleg Nesterov <oleg@redhat.com>
      Cc: Markus Metzger <markus.t.metzger@intel.com>
      Cc: Steven Rostedt <rostedt@goodmis.org>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      LKML-Reference: <20100325135413.938004390@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      faa4602e
    • P
      perf, x86: Clean up debugctlmsr bit definitions · 7c5ecaf7
      Peter Zijlstra 提交于
      Move all debugctlmsr thingies into msr-index.h
      Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl>
      LKML-Reference: <20100325135413.861425293@chello.nl>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      7c5ecaf7
    • C
      x86, perf: Add raw events support for the P4 PMU · d814f301
      Cyrill Gorcunov 提交于
      The adding of raw event support lead to complete code
      refactoring. I hope is became more readable then it was.
      
      The list of changes:
      
      1)  The 64bit config field is enough to hold all information we need
          to track event details. To achieve it we used *own* enum for
          events selection in ESCR register and map this key into proper
          value at moment of event enabling.
      
          For the same reason we use 12LSB bits in CCCR register -- to track
          which exactly cache trace event was requested. And we cear this bits
          at real 'write' moment.
      
      2)  There is no per-cpu area reserved for P4 PMU anymore. We
          don't need it. All is held by config.
      
      3)  Now we may use any available counter, ie we try to grab any
          possible counter.
      
      v2:
        - Lin Ming reported the lack of ESCR selector in CCCR for cache events
      
      v3:
        - Don't loose cache event codes at config unpacking procedure, we may
          need it one day so no obscure hack behind our back, better to clear
          reserved bits explicitly when needed (thanks Ming for pointing out)
      
        - Lin Ming fixed misplaced opcodes in cache events
      Signed-off-by: NCyrill Gorcunov <gorcunov@openvz.org>
      Tested-by: NLin Ming <ming.m.lin@intel.com>
      Signed-off-by: NLin Ming <ming.m.lin@intel.com>
      Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
      Cc: Stephane Eranian <eranian@google.com>
      Cc: Robert Richter <robert.richter@amd.com>
      Cc: Frederic Weisbecker <fweisbec@gmail.com>
      Cc: Cyrill Gorcunov <gorcunov@gmail.com>
      Cc: Peter Zijlstra <peterz@infradead.org>
      LKML-Reference: <1269403766.3409.6.camel@minggr.sh.intel.com>
      [ v4: did a few whitespace fixlets ]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      d814f301
  2. 19 3月, 2010 14 次提交
  3. 18 3月, 2010 1 次提交
  4. 17 3月, 2010 8 次提交
  5. 16 3月, 2010 10 次提交
  6. 15 3月, 2010 4 次提交