Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Add GPU family definitions and timeout value for IP components.
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Feel free to suggest more.
Signed-off-by: NMarek Olšák <marek.olsak@amd.com>
Acked-by: NMichel Dänzer <michel.daenzer@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

the definitions can be shared by different IP components.

v2: fix include path
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

We need to return the sequence number to userspace
even when we don't use user fences.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Added to:
- handle draining the ring on suspend
- properly enable/disable interrupts on suspend and resume

Fix breakages from:
commit 467ee3be53d240d08beed2e82a941e820c1ac323
Author: Chunming Zhou <david1.zhou@amd.com>
Date:   Mon Jun 1 14:14:32 2015 +0800

    drm/amdgpu: always enable EOP interrupt v2
Tested-by: NAudrey Grodzovsky <audrey.grodzovsky@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

v2 (chk): always enable EOP interrupt, independent of scheduler,
	  remove now unused delayed_irq handling.
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

This makes assigning VM IDs independent from the use of VM IDs.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

v2 (chk): split fix from original patch
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

Otherwise the first 16 fences of a context will always signal immediately.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>

It's not used any more.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChunming Zhou <david1.zhou@amd.com>

This is a prerequisite for the GPU scheduler to make the order
of submission independent from the order of execution.

v2: properly implement the locking
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChunming Zhou <david1.zhou@amd.com>

This also requires some error handling from the callers of that function.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChunming Zhou <david1.zhou@amd.com>

The comment is misleading and incorrect, remove it.

Printing the id is completely meaningless and this practice
can cause a race conditions on command submission.

The flags and hangs fields are completely unused.

Give all fields a common indentation.

v2: remove fpriv reference and unused flags as well, fix debug message.
Signed-off-by: NChristian König <christian.koenig@amd.com>
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChunming Zhou <david1.zhou@amd.com>

v3: check whether ip_blocks is enable
v2: add break in the for loop.
Signed-off-by: NRex zhu <rezhu@amd.com>

Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This new interface can be used by IP components to retrieve the
firmware information from the core driver.

v2: fix one typo
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NRex Zhu <Rex.Zhou@amd.com>
Signed-off-by: NYoung Yang <Young.Yang@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the cgs interface for allocating
GPU memory.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <david1.zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the interface for atombios command
and data table access.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the irq src registrar.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the pciconfig register accessors.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This implements the MMIO register accessors.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

CGS (Common Graphics Services) is an AMD cross component
abstraction layer to designed to better encapsulate
specific IP block drivers so different teams can effectively
work on differnet IP block drivers independently. It provides
a common interface for things like accessing registers,
allocating GPU memory, and registering interrupt sources.
The plan is to eventually move more and more IP drivers to
this interface.  The first user is the ACP IP driver.
Reviewed-by: NJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: NChunming Zhou <David1.Zhou@amd.com>
Acked-by: NChristian König <christian.koenig@amd.com>
Acked-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

In function 'amdgpu_uvd_cs_pass2':
warning: 'min_ctx_size' may be used uninitialized in this function
  buf_sizes[0x4] = min_ctx_size;
                 ^
note: 'min_ctx_size' was declared here
  unsigned image_size, tmp, min_dpb_size, num_dpb_buffer, min_ctx_size;
                                                          ^
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org

This reverts commit 78ad5cdd.
This commit breaks dpm and suspend/resume on CZ.

Signed-off-by: NBoyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Use the newly created wrapper drm_fb_helper functions instead of calling
core fbdev functions directly. They also simplify the fb_info creation.

v3:
- Don't touch remove_conflicting_framebuffers

v2:
- Fixed PTR_ERR issue mentioned by kbuild bot

Cc: Fengguang Wu <fengguang.wu@intel.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Oded Gabbay <oded.gabbay@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>

The fw_version and feature_verion should be set correctly when the
firmwares are loaded by SMU on Tonga/Carrzio/Iceland
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

Expose feature version to user space for RLC/MEC/MEC2 ucode as well

v2: fix coding style
Signed-off-by: NJammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

gfx_v7_0_print_status contains a for loop on variable queue which does
not update this variable between each iteration.  This is bug is
reported by clang while building allmodconfig LLVMLinux on x86_64:

    drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c:5126:19: error: variable
    'queue' used in loop condition not modified in loop body
    [-Werror,-Wloop-analysis]
                for (queue = 0; queue < 8; i++) {
                                ^~~~~

Fix this by incrementing variable queue instead of i in this loop.
Signed-off-by: NNicolas Iooss <nicolas.iooss_linux@m4x.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Always set num_rbs to 2 for CZ.  The 1 RB parts are often harvest
configs.  The will get sorted out in mesa when we program
PA_SC_RASTER_CONFIG[_1].
Acked-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

A logical AND operation was used during mask and shift, instead of a
bitwise AND operation. This patch fixes this bug by changing the
operation to bitwise AND.
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

The wrong define was used to check if the hqd is still active

v2: Don't use SHIFT as the MASK is already shifted
Signed-off-by: NOded Gabbay <oded.gabbay@gmail.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

hdp flush is not needed for IBs that dispatched from kernel inside
because there is no video memory host access
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

compute ring didn't use const engine byfar, so ignore CE things in
compute routine
Signed-off-by: Nmonk.liu <monk.liu@amd.com>
Reviewed-by: NChristian König <christian.koenig@amd.com>

We recently changed the drm_amdgpu_info_device struct so now there is
a 4 byte hole at the end.  We need to initialize it so we don't disclose
secret information from the stack.

Fixes: fa92754e ('drm/amdgpu: add VCE harvesting instance query')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

If we fail during device init, record what state each
block is in so that we can tear down clearly.

Fixes various problems on device init failure.
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>