1. 08 3月, 2018 1 次提交
  2. 06 3月, 2018 6 次提交
  3. 02 3月, 2018 12 次提交
    • G
      s390: Fix runtime warning about negative pgtables_bytes · 61e18270
      Guenter Roeck 提交于
      When running s390 images with 'compat' processes, the following
      BUG is seen repeatedly.
      
      BUG: non-zero pgtables_bytes on freeing mm: -16384
      
      Bisect points to commit b4e98d9a ("mm: account pud page tables").
      Analysis shows that init_new_context() is called with
      mm->context.asce_limit set to _REGION3_SIZE. In this situation,
      pgtables_bytes remains set to 0 and is not increased. The message is
      displayed when the affected process dies and mm_dec_nr_puds() is called.
      
      Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Fixes: b4e98d9a ("mm: account pud page tables")
      Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      61e18270
    • H
      parisc: Reduce irq overhead when run in qemu · 636a415b
      Helge Deller 提交于
      When run under QEMU, calling mfctl(16) creates some overhead because the
      qemu timer has to be scaled and moved into the register. This patch
      reduces the number of calls to mfctl(16) by moving the calls out of the
      loops.
      
      Additionally, increase the minimal time interval to 8000 cycles instead
      of 500 to compensate possible QEMU delays when delivering interrupts.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      Cc: stable@vger.kernel.org # 4.14+
      636a415b
    • H
      parisc: Use cr16 interval timers unconditionally on qemu · 5ffa8518
      Helge Deller 提交于
      When running on qemu we know that the (emulated) cr16 cpu-internal
      clocks are syncronized. So let's use them unconditionally on qemu.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      Cc: stable@vger.kernel.org # 4.14+
      5ffa8518
    • H
      parisc: Check if secondary CPUs want own PDC calls · 0ed1fe4a
      Helge Deller 提交于
      The architecture specification says (for 64-bit systems): PDC is a per
      processor resource, and operating system software must be prepared to
      manage separate pointers to PDCE_PROC for each processor.  The address
      of PDCE_PROC for the monarch processor is stored in the Page Zero
      location MEM_PDC. The address of PDCE_PROC for each non-monarch
      processor is passed in gr26 when PDCE_RESET invokes OS_RENDEZ.
      
      Currently we still use one PDC for all CPUs, but in case we face a
      machine which is following the specification let's warn about it.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      0ed1fe4a
    • H
      parisc: Hide virtual kernel memory layout · fd8d0ca2
      Helge Deller 提交于
      For security reasons do not expose the virtual kernel memory layout to
      userspace.
      Signed-off-by: NHelge Deller <deller@gmx.de>
      Suggested-by: NKees Cook <keescook@chromium.org>
      Cc: stable@vger.kernel.org # 4.15
      Reviewed-by: NKees Cook <keescook@chromium.org>
      fd8d0ca2
    • J
      parisc: Fix ordering of cache and TLB flushes · 0adb24e0
      John David Anglin 提交于
      The change to flush_kernel_vmap_range() wasn't sufficient to avoid the
      SMP stalls.  The problem is some drivers call these routines with
      interrupts disabled.  Interrupts need to be enabled for flush_tlb_all()
      and flush_cache_all() to work.  This version adds checks to ensure
      interrupts are not disabled before calling routines that need IPI
      interrupts.  When interrupts are disabled, we now drop into slower code.
      
      The attached change fixes the ordering of cache and TLB flushes in
      several cases.  When we flush the cache using the existing PTE/TLB
      entries, we need to flush the TLB after doing the cache flush.  We don't
      need to do this when we flush the entire instruction and data caches as
      these flushes don't use the existing TLB entries.  The same is true for
      tmpalias region flushes.
      
      The flush_kernel_vmap_range() and invalidate_kernel_vmap_range()
      routines have been updated.
      
      Secondly, we added a new purge_kernel_dcache_range_asm() routine to
      pacache.S and use it in invalidate_kernel_vmap_range().  Nominally,
      purges are faster than flushes as the cache lines don't have to be
      written back to memory.
      
      Hopefully, this is sufficient to resolve the remaining problems due to
      cache speculation.  So far, testing indicates that this is the case.  I
      did work up a patch using tmpalias flushes, but there is a performance
      hit because we need the physical address for each page, and we also need
      to sequence access to the tmpalias flush code.  This increases the
      probability of stalls.
      
      Signed-off-by: John David Anglin <dave.anglin@bell.net>
      Cc: stable@vger.kernel.org # 4.9+
      Signed-off-by: NHelge Deller <deller@gmx.de>
      0adb24e0
    • M
      sh: fix build error for empty CONFIG_BUILTIN_DTB_SOURCE · 1b1e4ee8
      Masahiro Yamada 提交于
      If CONFIG_USE_BUILTIN_DTB is enabled, but CONFIG_BUILTIN_DTB_SOURCE
      is empty (for example, allmodconfig), it fails to build, like this:
      
        make[2]: *** No rule to make target 'arch/sh/boot/dts/.dtb.o',
        needed by 'arch/sh/boot/dts/built-in.o'.  Stop.
      
      Surround obj-y with ifneq ... endif.
      
      I replaced $(CONFIG_USE_BUILTIN_DTB) with 'y' since this is always
      the case from the following code from arch/sh/Makefile:
      
        core-$(CONFIG_USE_BUILTIN_DTB)  += arch/sh/boot/dts/
      Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
      1b1e4ee8
    • R
      KVM: x86: fix vcpu initialization with userspace lapic · b7e31be3
      Radim Krčmář 提交于
      Moving the code around broke this rare configuration.
      Use this opportunity to finally call lapic reset from vcpu reset.
      
      Reported-by: syzbot+fb7a33a4b6c35007a72b@syzkaller.appspotmail.com
      Suggested-by: NPaolo Bonzini <pbonzini@redhat.com>
      Fixes: 0b2e9904 ("KVM: x86: move LAPIC initialization after VMCS creation")
      Cc: stable@vger.kernel.org
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      b7e31be3
    • W
      KVM: X86: Allow userspace to define the microcode version · 518e7b94
      Wanpeng Li 提交于
      Linux (among the others) has checks to make sure that certain features
      aren't enabled on a certain family/model/stepping if the microcode version
      isn't greater than or equal to a known good version.
      
      By exposing the real microcode version, we're preventing buggy guests that
      don't check that they are running virtualized (i.e., they should trust the
      hypervisor) from disabling features that are effectively not buggy.
      Suggested-by: NFilippo Sironi <sironi@amazon.de>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Liran Alon <liran.alon@oracle.com>
      Cc: Nadav Amit <nadav.amit@gmail.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NWanpeng Li <wanpengli@tencent.com>
      Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      518e7b94
    • W
      KVM: X86: Introduce kvm_get_msr_feature() · 66421c1e
      Wanpeng Li 提交于
      Introduce kvm_get_msr_feature() to handle the msrs which are supported
      by different vendors and sharing the same emulation logic.
      
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Liran Alon <liran.alon@oracle.com>
      Cc: Nadav Amit <nadav.amit@gmail.com>
      Cc: Borislav Petkov <bp@alien8.de>
      Cc: Tom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NWanpeng Li <wanpengli@tencent.com>
      Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      66421c1e
    • T
      KVM: SVM: Add MSR-based feature support for serializing LFENCE · d1d93fa9
      Tom Lendacky 提交于
      In order to determine if LFENCE is a serializing instruction on AMD
      processors, MSR 0xc0011029 (MSR_F10H_DECFG) must be read and the state
      of bit 1 checked.  This patch will add support to allow a guest to
      properly make this determination.
      
      Add the MSR feature callback operation to svm.c and add MSR 0xc0011029
      to the list of MSR-based features.  If LFENCE is serializing, then the
      feature is supported, allowing the hypervisor to set the value of the
      MSR that guest will see.  Support is also added to write (hypervisor only)
      and read the MSR value for the guest.  A write by the guest will result in
      a #GP.  A read by the guest will return the value as set by the host.  In
      this way, the support to expose the feature to the guest is controlled by
      the hypervisor.
      Reviewed-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      d1d93fa9
    • T
      KVM: x86: Add a framework for supporting MSR-based features · 801e459a
      Tom Lendacky 提交于
      Provide a new KVM capability that allows bits within MSRs to be recognized
      as features.  Two new ioctls are added to the /dev/kvm ioctl routine to
      retrieve the list of these MSRs and then retrieve their values. A kvm_x86_ops
      callback is used to determine support for the listed MSR-based features.
      Signed-off-by: NTom Lendacky <thomas.lendacky@amd.com>
      Signed-off-by: NPaolo Bonzini <pbonzini@redhat.com>
      [Tweaked documentation. - Radim]
      Signed-off-by: NRadim Krčmář <rkrcmar@redhat.com>
      801e459a
  4. 01 3月, 2018 7 次提交
  5. 28 2月, 2018 7 次提交
  6. 27 2月, 2018 5 次提交
  7. 24 2月, 2018 2 次提交