Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 161
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
  1. 01 5月, 2005 32 次提交
  3. 30 4月, 2005 8 次提交
    • R
      [PATCH] ARM: PXA I2C: add platform device · bb9bffcb
      由 Russell King 提交于 
      Add the PXA I2C platform device.
Signed-off-by: NRussell King <rmk@arm.linux.org.uk>
      bb9bffcb
    • R
      [PATCH] ARM: RTC: allow driver methods to return error · d5aa207e
      由 Russell King 提交于 
      Allow RTC drivers to return error codes from their read_time
or read_alarm methods.
Signed-off-by: NRussell King <rmk@arm.linux.org.uk>
      d5aa207e
    • L
      [PATCH] ARM: 2660/2: fix ixdp2800 boot and pci init · 53e173f6
      由 Lennert Buytenhek 提交于 
      Patch from Lennert Buytenhek

The IXDP2800 is an evalution platform for the IXP2800 processor that
has two IXP2800s connected to the same PCI bus.  This is problematic
as both CPUs will try to configure the PCI bus as they boot linux.
Contrary to on the other IXP2000 platforms, the boot loader on the
IXDP2800 doesn't configure the PCI bus properly, so we do want the
linux instance on one of the CPUs to do that.
Making one of the CPUs ignore the PCI bus (and thus act like a pure
PCI slave device) is not an option because there is a 82559 NIC on
the PCI bus for each of the CPUs.
The chosen solution is to have the master CPU configure the PCI bus
while the slave is kept in a quiescent state, and then to have the
slave CPU scan the PCI bus (without assigning resources) while the
master is kept in a quiescent state.  After this ritual, the master
deletes the slave NIC from its PCI device list, the slave deletes
the master NIC from its device list, and (almost) all is well.
There's still one little problem: each of the CPUs has a 1G SDRAM
BAR, but the IXP2000 only has 512M of outbound PCI memory window.
We solve this by hand-assigning the master and slave SDRAM BARs to
a location outside each of the IXP's outbound PCI windows, and by
having the rest of the BARs autoconfigured in the outbound PCI
windows, in the range [e0000000..ffffffff], so that there is a 1:1
pci:phys mapping between them.
Even with this patch, a number of issues still remain -- just imagine
what happens if one of the CPUs is rebooted, by watchdog or by hand,
but the other one isn't.  But those issues are not easily fixable
given the strange PCI layout of this board and the behavior of the
boot loader shipped with the platform.

Signed-off-by: Lennert Buytenhek
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      53e173f6
    • G
      [PATCH] ARM: 2656/1: Access permission bits are wrong for kernel XIP sections on ARMv6 · ca315159
      由 George G. Davis 提交于 
      Patch from George G. Davis

This patch is required for kernel XIP support on ARMv6 machines.  It ensures that the access permission bits for kernel XIP section descriptors are APX=1 and AP[1:0]=01, which is Kernel read-only/User no access permissions.  Prior to this change, kernel XIP section descriptor access permissions were set to Kernel no access/User no access on ARMv6 machines and the kernel would therefore hang upon entry to userspace when set_fs(USER_DS) was executed.

Signed-off-by: Steve Longerbeam
Signed-off-by: George G. Davis
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ca315159
    • N
      [PATCH] ARM: 2651/3: kernel helpers for NPTL support · 2d2669b6
      由 Nicolas Pitre 提交于 
      Patch from Nicolas Pitre

This patch entirely reworks the kernel assistance for NPTL on ARM.
In particular this provides an efficient way to retrieve the TLS
value and perform atomic operations without any instruction emulation
nor special system call.  This even allows for pre ARMv6 binaries to
be forward compatible with SMP systems without any penalty.
The problematic and performance critical operations are performed
through segment of kernel provided user code reachable from user space
at a fixed address in kernel memory.  Those fixed entry points are
within the vector page so we basically get it for free as no extra
memory page is required and nothing else may be mapped at that
location anyway.
This is different from (but doesn't preclude) a full blown VDSO
implementation, however a VDSO would prevent some assembly tricks with
constants that allows for efficient branching to those code segments.
And since those code segments only use a few cycles before returning to
user code, the overhead of a VDSO far call would add a significant
overhead to such minimalistic operations.
The ARM_NR_set_tls syscall also changed number.  This is done for two
reasons:
1) this patch changes the way the TLS value was previously meant to be
   retrieved, therefore we ensure whatever library using the old way
   gets fixed (they only exist in private tree at the moment since the
   NPTL work is still progressing).
2) the previous number was allocated in a range causing an undefined
   instruction trap on kernels not supporting that syscall and it was
   determined that allocating it in a range returning -ENOSYS would be
   much nicer for libraries trying to determine if the feature is
   present or not.

Signed-off-by: Nicolas Pitre
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      2d2669b6
    • G
      [PATCH] ARM: 2655/1: ARM1136 SWP instruction abort handler fix · 3a1e5015
      由 George G. Davis 提交于 
      Patch from George G. Davis

As noted in http://www.arm.com/linux/patch-2.6.9-arm1.gz, the "Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR." So the v6_early_abort handler does not report the correct rd/wr direction for the SWP instruction which may result in SEGVS or hangs. In order to work around this problem, this patch merely updates the fix contained in the ARM Ltd. patch to use the macroised abort handler fixups.

Signed-off-by: George G. Davis
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      3a1e5015
    • L
      [PATCH] ARM: 2659/1: do not assign PCI I/O address zero on IXP2000 · 458a83fa
      由 Lennert Buytenhek 提交于 
      Patch from Lennert Buytenhek

Assigning the address zero to a PCI device BAR causes some part of the
PCI subsystem to believe that resource allocation for that BAR failed
due to resource conflicts, which will make attempts to enable the
device fail.  Work around this by assigning I/O addresses starting
from 00010000.
While we're at it, make the PCI I/O resource end at 0001ffff, since we
only have 64k of outbound I/O window on the IXP2000, and we don't do
bank switching.

Signed-off-by: Lennert Buytenhek
Signed-off-by: Deepak Saxena
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      458a83fa
    • L
      [PATCH] ARM: 2658/1: start ixp2000 pci memory resource at 0xe0000000 · ae36bf58
      由 Lennert Buytenhek 提交于 
      Patch from Lennert Buytenhek

On the IXDP2800, the bootloader does an awful job of configuring
the PCI bus, so we make linux reconfigure everything.  Having a 1:1
pci:phys address mapping generally simplifies everything, so try to
allocate PCI addresses from the [e0000000..ffffffff] range, which is
the physical address range of the outbound PCI window on the IXP2000.
This does not affect any of the other IXP2000 platforms since they
all use their bootloader's PCI resource assignment.

Signed-off-by: Lennert Buytenhek
Signed-off-by: Deepak Saxena
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      ae36bf58