The dmi-sysfs module adds DMI table structures entries under
/sys/firmware/dmi/entries only, so rename documentation file to
sysfs-firmware-dmi-entries as more appropriate. Without renaming it's
confusing to differ this from sysfs-firmware-dmi-tables that adds raw
DMI table and actually adds "dmi" kobject.
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@globallogic.com>
Signed-off-by: NJean Delvare <jdelvare@suse.de>

Some utils, like dmidecode and smbios, need to access SMBIOS entry
table area in order to get information like SMBIOS version, size, etc.
Currently it's done via /dev/mem. But for situation when /dev/mem
usage is disabled, the utils have to use dmi sysfs instead, which
doesn't represent SMBIOS entry and adds code/delay redundancy when direct
access for table is needed.

So this patch creates dmi/tables and adds SMBIOS entry point to allow
utils in question to work correctly without /dev/mem. Also patch adds
raw dmi table to simplify dmi table processing in user space, as
proposed by Jean Delvare.
Tested-by: NRoy Franz <roy.franz@linaro.org>
Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@globallogic.com>
Signed-off-by: NJean Delvare <jdelvare@suse.de>

There is a very subtle difference between mmap()+mlock() vs
mmap(MAP_LOCKED) semantic.  The former one fails if the population of the
area fails while the later one doesn't.  This basically means that
mmap(MAPLOCKED) areas might see major fault after mmap syscall returns
which is not the case for mlock.  mmap man page has already been altered
but Documentation/vm/unevictable-lru.txt deserves a clarification as well.
Signed-off-by: NMichal Hocko <mhocko@suse.cz>
Reported-by: NDavid Rientjes <rientjes@google.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Change the default behavior of watchdog so it only runs on the
housekeeping cores when nohz_full is enabled at build and boot time.
Allow modifying the set of cores the watchdog is currently running on
with a new kernel.watchdog_cpumask sysctl.

In the current system, the watchdog subsystem runs a periodic timer that
schedules the watchdog kthread to run.  However, nohz_full cores are
designed to allow userspace application code running on those cores to
have 100% access to the CPU.  So the watchdog system prevents the
nohz_full application code from being able to run the way it wants to,
thus the motivation to suppress the watchdog on nohz_full cores, which
this patchset provides by default.

However, if we disable the watchdog globally, then the housekeeping
cores can't benefit from the watchdog functionality.  So we allow
disabling it only on some cores.  See Documentation/lockup-watchdogs.txt
for more information.

[jhubbard@nvidia.com: fix a watchdog crash in some configurations]
Signed-off-by: NChris Metcalf <cmetcalf@ezchip.com>
Acked-by: NDon Zickus <dzickus@redhat.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Ulrich Obergfell <uobergfe@redhat.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Signed-off-by: NJohn Hubbard <jhubbard@nvidia.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Do some initial cleanup, more probably will come.

- Move credits section to the end
- Update maintainers
- Drop sourceforge reference - project is long upstream now
- Reformat sections
- Reformat paragraphs
- Clarify text
- Bring it up-to-date
- Drop useless "future hardware scanning" section
Signed-off-by: NBorislav Petkov <bp@suse.de>

Fix various typos in Documentation/edac.txt.
Signed-off-by: NRami Rosen <ramirose@gmail.com>
Link: http://lkml.kernel.org/r/1434694714-2924-1-git-send-email-ramirose@gmail.comSigned-off-by: NBorislav Petkov <bp@suse.de>

Add support for the Arria10 SDRAM EDAC. Update the bindings document for
the new match string.
Signed-off-by: NThor Thayer <tthayer@opensource.altera.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: galak@codeaurora.org
Cc: grant.likely@linaro.org
Cc: ijc+devicetree@hellion.org.uk
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: m.chehab@samsung.com
Cc: mark.rutland@arm.com
Cc: pawel.moll@arm.com
Cc: robh+dt@kernel.org
Cc: tthayer.linux@gmail.com
Link: http://lkml.kernel.org/r/1433428128-7292-5-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>

Simple LAN device for debug or management purposes.
Device supports interrupts for RX and TX(completion).
Device does not have DMA ability.
Signed-off-by: NNoam Camus <noamc@ezchip.com>
Signed-off-by: NTal Zilcer <talz@ezchip.com>
Acked-by: NAlexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add constants and callback functions for the dwmac on rk3368 socs.
As can be seen, the base structure is the same, only registers and
the bits in them moved slightly.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NWei Fang <fangwei1@huawei.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Add sama5d2 to the biding documentation for this use of the GEM IP.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

On sama5d4, we only have a GEM IP that is configured to do 10/100 Mbits. So the
use of "Gigabit" can be confusing.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

In the driver and the DT bindings we use the "atmel" prefix. Fix it in the
binding documentation.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>

h8300_timer8: 8bit clockevent device
h8300_timer16 / h8300_tpu: 16bit clocksource
Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/mic/mpssd/mpssd.c:93:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:96:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:113:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:116:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:119:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:119:3: error: (near initialization for 'virtnet_dev_page.host_features')
Documentation/mic/mpssd/mpssd.c:146:10: error: braced-group within expression allowed only inside a function
Documentation/mic/mpssd/mpssd.c:149:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:149:3: error: (near initialization for 'virtblk_dev_page.host_features')
Documentation/mic/mpssd/mpssd.c:151:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:151:3: error: (near initialization for 'virtblk_dev_page.blk_config.seg_max')
Documentation/mic/mpssd/mpssd.c:152:3: error: initializer element is not constant
Documentation/mic/mpssd/mpssd.c:152:3: error: (near initialization for 'virtblk_dev_page.blk_config.capacity')
make[5]: *** [Documentation/mic/mpssd/mpssd.o] Error 1

Since it is building /usr/sbin/mpssd and /usr/sbin/micctrl
for x86_64 and the original authors indicated[1] that:

   MIC card is expected to work with x86_64 host, not with ppc64.
   We have never compiled on ppc host..

so it probably makes sense to just skip building these userspace
programs when we are cross compiling.

[1] https://lists.ozlabs.org/pipermail/linuxppc-dev/2014-December/123296.html

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Sudeep Dutt <sudeep.dutt@intel.com>
Cc: Caz Yokoyama <Caz.Yokoyama@intel.com>
Cc: linux-doc@vger.kernel.org
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/prctl/disable-tsc-on-off-stress-test.c:36:1: error:
 impossible register constraint in 'asm'
Documentation/prctl/disable-tsc-ctxt-sw-stress-test.c:34:1: error:
 impossible register constraint in 'asm'
Documentation/prctl/disable-tsc-test.c:36:1: error: impossible
 register constraint in 'asm'

It probably makes sense to just skip building these tests when
we are cross compiling.

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: Erik Bosman <ejbosman@cs.vu.nl>
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The following was seen in linux-next build coverage, which is somewhat
unique since it uses powerpc host to cross compile x86:

Documentation/vDSO/vdso_standalone_test_x86.c:49:2: error: impossible
register constraint in 'asm'
make[4]: *** [Documentation/vDSO/vdso_standalone_test_x86.o] Error 1

It probably makes sense to just skip building these tests when
we are cross compiling.

Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: Andy Lutomirski <luto@amacapital.net>
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

This patch fix some spelling typo in sysfs-bus-fcoe
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Recently wikipedia announced to secure access to the servers.
Now all http access re-route to https.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

Recently wikipedia announced to secure access to the servers.
Now all http access re-route to https.
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The PCI based UART can be specified for earlyprintk with the 'pciserial'
parameter from the ea9e9d80. This patch adds missing information about
this parameter.
Signed-off-by: NAlexander Kuleshov <kuleshovmail@gmail.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

This patch fix a spelling typo in Documentation/pps/pps.txt
Signed-off-by: NMasanari Iida <standby24x7@gmail.com>
Acked-by: NRodolfo Giometti <giometti@enneenne.com>
[jc: did s/into/in the/ on the same line while we were there]
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

The header install makefile creates an 'include' directory inside
INSTALL_HDR_PATH and appending include to the path results in headers
being installed to include/include.

Don't recommend appending include to the path as makefile already does
this.
Signed-off-by: NAnish Bhatt <anish@chelsio.com>
Signed-off-by: NJonathan Corbet <corbet@lwn.net>

On few platforms, for power efficiency, we want the device to be
configured for a specific OPP while we put the device in suspend state.

Add an optional property in operating-points-v2 bindings for that.
Suggested-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

On some platforms (Like Qualcomm's SoCs), it is not decided until
runtime on what OPPs to use. The OPP tables can be fixed at compile
time, but which table to use is found out only after reading some efuses
(sort of an prom) and knowing characteristics of the SoC.

To support such platform we need to pass multiple OPP tables per device
and hardware should be able to choose one and only one table out of
those.

Update operating-points-v2 bindings to support that.
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Current OPP (Operating performance point) device tree bindings have been
insufficient due to the inflexible nature of the original bindings. Over
time, we have realized that Operating Performance Point definitions and
usage is varied depending on the SoC and a "single size (just frequency,
voltage) fits all" model which the original bindings attempted and
failed.

The proposed next generation of the bindings addresses by providing a
expandable binding for OPPs and introduces the following common
shortcomings seen with the original bindings:

- Getting clock/voltage/current rails sharing information between CPUs.
  Shared by all cores vs independent clock per core vs shared clock per
  cluster.

- Support for specifying current levels along with voltages.

- Support for multiple regulators.

- Support for turbo modes.

- Other per OPP settings: transition latencies, disabled status, etc.?

- Expandability of OPPs in future.

This patch introduces new bindings "operating-points-v2" to get these problems
solved. Refer to the bindings for more details.

We now have multiple versions of OPP binding and only one of them should
be used per device.
Signed-off-by: NViresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Acked-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

Add device tree bindings for the DA9063 OnKey driver.
Signed-off-by: NSteve Twiss <stwiss.opensource@diasemi.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NRichard Fitzgerald <rf@opensource.wolfsonmicro.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Fix typo in 'Multifunction'.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

This patch adds device tree binding documentation for
the flash cell of the Maxim max77693 multifunctional device.
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>
Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add hwmon driver for the Microchip TC74.

The TC74 is a single-input 8-bit I2C temperature sensor,
with +-2 degrees centigrade accuracy.
Signed-off-by: NMaciej Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Add DT bindings documentation for the new marvell-cesa driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

We are about to add a new driver to support new features like using the
TDMA engine to offload the CPU.
Orion, Dove and Kirkwood platforms are already using the mv_cesa driver,
but Orion SoCs do not embed the TDMA engine, which means we will have to
differentiate them if we want to get TDMA support on Dove and Kirkwood.
In the other hand, the migration from the old driver to the new one is not
something all people are willing to do without first auditing the new
driver.
Hence we have to support the new compatible in the mv_cesa driver so that
new platforms with updated DTs can still attach their crypto engine device
to this driver.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

The mv_cesa driver currently expects the SRAM memory region to be passed
as a platform device resource.

This approach implies two drawbacks:
- the DT representation is wrong
- the only one that can access the SRAM is the crypto engine

The last point is particularly annoying in some cases: for example on
armada 370, a small region of the crypto SRAM is used to implement the
cpuidle, which means you would not be able to enable both cpuidle and the
CESA driver.

To address that problem, we explicitly define the SRAM device in the DT
and then reference the sram node from the crypto engine node.

Also note that the old way of retrieving the SRAM memory region is still
supported, or in other words, backward compatibility is preserved.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

On Dove platforms, the crypto engine requires a clock. Document this
clocks property in the mv_cesa bindings doc.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NHerbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>