- 21 6月, 2015 2 次提交
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由 Thomas Abraham 提交于
With the addition of the new Samsung specific cpu-clock type, the arm clock can be represented as a cpu-clock type. Add the CPU clock configuration data and instantiate the CPU clock type for Exynos4210. Changes by Bartlomiej: - fixed issue with wrong dividers being setup by Common Clock Framework (by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock, without this change cpufreq-dt driver showed ~10 mA larger energy consumption when compared to cpufreq-exynos one when "performance" cpufreq governor was used on Exynos4210 SoC based Origen board), this was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in "[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update clock flags") but using these flags is not sufficient to fix the issue observed - removed Exynos5250 and Exynos5420 support for now Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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由 Thomas Abraham 提交于
The CPU clock provider supplies the clock to the CPU clock domain. The composition and organization of the CPU clock provider could vary among Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers and gates. This patch defines a new clock type for CPU clock provider and adds infrastructure to register the CPU clock providers for Samsung platforms. Changes by Bartlomiej: - fixed issue with setting lower dividers before the parent clock speed was lowered (the issue resulted in lockup on Exynos4210 SoC based Origen board when "ondemand" cpufreq governor was stress tested) - fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change() problem by moving cfg_data search outside of the spin locked area - removed leftover kfree() in exynos_register_cpu_clock() that could result in dereferencing the NULL pointer on error - moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers - added missing "last chance" checks to wait_until_divider_stable() and wait_until_mux_stable() (needed in case that IRQ handling took long time to proceed and resulted in function printing incorrect error message about timeout) - moved E4210_CPU_DIV[0,1]() macros just before their only users, this resulted in moving them from patch #2 to patch #3/6 ("clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock") - removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV() macros for now - added my Copyrights to drivers/clk/samsung/clk-cpu.c Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Mike Turquette <mturquette@linaro.org> Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: NThomas Abraham <thomas.ab@samsung.com> Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
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- 10 6月, 2015 4 次提交
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由 Jonghwa Lee 提交于
This patch adds 'CLK_IGNORE_UNUSED' flag to clocks which is required for operation of secure monitor call (smc). System will hang when it executes 'smc' with one of those clock is gated. All related clocks must be enabled. Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Joonyoung Shim 提交于
This patch adds the CLK_SET_RATE_PARENT flag for 'aclk_g3d' clock and parent clocks becuase 'aclk_g3d' is used to change GPU frequency for DVFS (Dynamic Voltage Frequency Scaling) feature and adds CLK_IGNORE_UNUSED flags to 'aclk_asyncapbs_g3d'/'aclk_asyncapbm_g3d' clocks to access the SFR of the MALI device. Signed-off-by: NJoonyoung Shim <jy0922.shim@samsung.com> [cw00.choi: Add patch description and add CLK_SET_RATE_PARENT to 'aclk_g3d' clk] Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Hyungwon Hwang 提交于
This DIV_CPIF register must be stored when the system is suspended, and must be restored on system resume. This patch adds the register to the list of restored registers. Signed-off-by: NHyungwon Hwang <human.hwang@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds CLK_SET_RATE_PARENT flag to support DVFS of Cortex-{A53|A57} core (big.LITTLE core) because 'sclk_{apollo|atlas}' leaf clock is used to change the CPU frequency of Cortex-{A53|A57} core in arm_big_little.c driver. - 'apollo' word means the LITTLE core (Cortex-A53 core) in Exynos5433 TRM. - 'atlas' word means the big core (Cortex-A57 core) in Exynos5433 TRM. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 05 6月, 2015 1 次提交
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由 Uwe Kleine-König 提交于
Since commit 2893c379 ("clk: make strings in parent name arrays const") the name of parent clocks can be const. So add more const in several clock drivers. Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 22 5月, 2015 1 次提交
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由 Shailendra Verma 提交于
Signed-off-by: NShailendra Verma <shailendra.capricorn@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 15 5月, 2015 1 次提交
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由 Stephen Boyd 提交于
drivers/clk/samsung/clk-exynos5260.c:138:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:328:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:392:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:494:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:583:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:644:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:779:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:898:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:962:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:1018:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:1165:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:1373:40: warning: Using plain integer as NULL pointer drivers/clk/samsung/clk-exynos5260.c:1829:40: warning: Using plain integer as NULL pointer Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 06 5月, 2015 3 次提交
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由 Krzysztof Kozlowski 提交于
The platform_device_id is not modified by the driver and core uses it as const. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Krzysztof Kozlowski 提交于
Staticize symbols not exported and not used outside of file. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Krzysztof Kozlowski 提交于
Add missing static to local (file-scope only) symbols. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 05 5月, 2015 1 次提交
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由 Javier Martinez Canillas 提交于
Commit ae43b328 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") added pm support for the pl330 dma driver but it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated during suspend and this in turn makes its parent clock aclk266_g2d to be gated. But the clock needs to be ungated prior suspend to allow the system to be suspend and resumed correctly. Add GATE_BUS_TOP register to the list of registers to be restored when the system enters into a suspend state so aclk266_g2d will be ungated. Thanks to Abhilash Kesavan for figuring out that this was the issue. Fixes: ae43b328 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12") Cc: stable@vger.kernel.org # 3.19+ Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: NKevin Hilman <khilman@linaro.org> Tested-by: NAbhilash Kesavan <a.kesavan@samsung.com> Acked-by: NTomasz Figa <tomasz.figa@gmail.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 29 4月, 2015 5 次提交
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由 Chanwoo Choi 提交于
This patch fixes the wrong PMS value of exynos5433_pll_rates table for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL. - 720 MHz (mdiv=360, pdiv=6, sdiv=1) -> 700 MHz (mdiv=175, pdiv=3, sdiv=1) - 350 MHz (mdiv=360, pdiv=6, sdiv=2) -> (mdiv=350, pdiv=6, sdiv=2) - 133 MHz (mdiv=552, pdiv=6, sdiv=4) -> (mdiv=532, pdiv=6, sdiv=4) Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch fixes the wrong parent clock of sclk_apollo clock from 'div_apollo_pll' to 'div_apollo2'. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Jonghwa Lee 提交于
CLK_PCLK_MONOTONIC_CNT clock had a wrong register assigned to it. The correct register is ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT. Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Jonghwa Lee 提交于
This patch fixes the wrong offoset of PCLK_MSCL_SECURE_SMMU_JPEG in CMU_MSCL domain. Fixes: b274bbfd (clk: samsung: exynos5433: Add clocks for CMU_MSCL domain) Signed-off-by: NJonghwa Lee <jonghwa3.lee@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Reviewed-by: NKrzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch removes the CONFIG_ARCH_EXYNOS5433 and then use only the CONFIG_ARCH_EXYNOS for ARM-64bit Exynos5433 SoC. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 13 4月, 2015 2 次提交
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Commit 42773b28 ("clk: samsung: exynos4: Enable ARMCLK down feature") enabled ARMCLK down feature on all Exynos4 SoCs. Unfortunately on Exynos4210 SoC ARMCLK down feature causes a lockup when ondemand cpufreq governor is used. Fix it by limiting ARMCLK down feature to Exynos4x12 SoCs. This patch was tested on: - Exynos4210 SoC based Trats board - Exynos4210 SoC based Origen board - Exynos4412 SoC based Trats2 board - Exynos4412 SoC based Odroid-U3 board Cc: Daniel Drake <drake@endlessm.com> Cc: Tomasz Figa <t.figa@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Fixes: 42773b28 ("clk: samsung: exynos4: Enable ARMCLK down feature") Cc: <stable@vger.kernel.org> # v3.17+ Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Uwe Kleine-König 提交于
The statement static const char *name[]; defines a modifiable array of pointers to constant chars. That is *name[0] = 'f'; is forbidden, but name[0] = "f"; is not. So marking an array that is defined as above with __initconst is wrong. Either an additional const must be added such that the whole definition reads: static const char *const name[] __initconst; or where this is not possible __initdata must be used. Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 31 3月, 2015 2 次提交
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由 Tomasz Figa 提交于
Add clock controller for CMU ISP clock domain on Exynos3250, providing clocks for FIMC-IS subsystem. [b.michalska: use samsung_cmu_register_one to register the provider; updated DT binding documentation] Signed-off-by: NTomasz Figa <t.figa@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NBeata Michalska <b.michalska@samsung.com> Acked-by: NKyungmin Park <kyungmin.park@samsung.com> [s.nawrocki: added __init attribute which was missing in function exynos3250_cmu_platform_init() in function, which has been] Reported-by: Nkbuild test robot <fengguang.wu@intel.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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由 Inha Song 提交于
This patch add CLKOUT driver support for Exynos3250 SoC. Exynos3250 SoC PMU_DEBUG is the same with Exynos4's PMU_DEBUG including CLKOUT mux. So we can use the exynos4's clkout init function for Exynos3250 without the need to add new function. Signed-off-by: NInha Song <ideal.song@samsung.com> Acked-by: NStephen Boyd <sboyd@codeaurora.org> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMichael Turquette <mturquette@linaro.org>
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- 06 2月, 2015 9 次提交
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由 Chanwoo Choi 提交于
This patch fixes the bug of CLK_SCLK_HDMI_SPDIF_DISP clock because this clock should be included in CMU_TOP domain. So, this patch moves the CLK_SCLK_HDMI_ SPDIF_DISP clock from CMU_MIF to CMU_TOP domain. Reported-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Inha Song 提交于
This patch add CLKOUT driver support for Exynos5433 SoC. Signed-off-by: NInha Song <ideal.song@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_CAM1 domain which generates the clocks for Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_CAM0 domain which generates the clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_ISP domain which generates the clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_HEVC domain which generates the clocks for HEVC(High Efficiency Video Codec) decoder IP. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_MFC domain which generates the clocks for MFC(Multi-Format Codec) IP. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_MSCL domain which generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_ATLAS domain which generates the clocks for Cortex-A57 Quad-core processsor, L2 cache controller and CoreSight. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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- 05 2月, 2015 9 次提交
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_APOLLO domain which generates the clocks for Cortex-A53 Quad-core processsor. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> [s.nawrocki@samsung.com: Renamed pclk_pmu_sysreg_apollo to pclk_sysreg_apollo] Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler clocks. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains the clocks for GPU(3D Graphics Engine). Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains which contain global data buses clocked at up the 400MHz. These blocks transfer data between DRAM and various sub-blocks. These clock domains also contain global peripheral buses clocked at 67/111/200/222/266/333/400 MHz and used for register accesses. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks for CMU_AUD domain which includes the clocks of Cortex-A5/Bus/Audio clocks. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER). Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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由 Chanwoo Choi 提交于
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in the CMU_TOP domain. Hence this patch adds G2D related clocks to the CMU_TOP domain. Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com> Acked-by: NInki Dae <inki.dae@samsung.com> Reviewed-by: NPankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
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