1. 03 7月, 2006 1 次提交
  2. 01 7月, 2006 1 次提交
  3. 29 6月, 2006 1 次提交
  4. 28 6月, 2006 2 次提交
  5. 21 6月, 2006 2 次提交
  6. 15 6月, 2006 1 次提交
    • P
      powerpc: Use 64k pages without needing cache-inhibited large pages · bf72aeba
      Paul Mackerras 提交于
      Some POWER5+ machines can do 64k hardware pages for normal memory but
      not for cache-inhibited pages.  This patch lets us use 64k hardware
      pages for most user processes on such machines (assuming the kernel
      has been configured with CONFIG_PPC_64K_PAGES=y).  User processes
      start out using 64k pages and get switched to 4k pages if they use any
      non-cacheable mappings.
      
      With this, we use 64k pages for the vmalloc region and 4k pages for
      the imalloc region.  If anything creates a non-cacheable mapping in
      the vmalloc region, the vmalloc region will get switched to 4k pages.
      I don't know of any driver other than the DRM that would do this,
      though, and these machines don't have AGP.
      
      When a region gets switched from 64k pages to 4k pages, we do not have
      to clear out all the 64k HPTEs from the hash table immediately.  We
      use the _PAGE_COMBO bit in the Linux PTE to indicate whether the page
      was hashed in as a 64k page or a set of 4k pages.  If hash_page is
      trying to insert a 4k page for a Linux PTE and it sees that it has
      already been inserted as a 64k page, it first invalidates the 64k HPTE
      before inserting the 4k HPTE.  The hash invalidation routines also use
      the _PAGE_COMBO bit, to determine whether to look for a 64k HPTE or a
      set of 4k HPTEs to remove.  With those two changes, we can tolerate a
      mix of 4k and 64k HPTEs in the hash table, and they will all get
      removed when the address space is torn down.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      bf72aeba
  7. 19 5月, 2006 5 次提交
  8. 03 5月, 2006 1 次提交
    • P
      [PATCH] powerpc: Use the ibm,pa-features property if available · d205819e
      Paul Mackerras 提交于
      Forthcoming IBM machines will have a "ibm,pa-features" property on CPU
      nodes, that contains bits indicating which optional architecture
      features are implemented by the CPU.  This adds code to use the
      property, if present, to update our CPU feature bitmaps.  Note that
      this means we can both set and clear feature bits based on what
      the firmware tells us.
      
      This is based on a patch by Will Schmidt <willschm@us.ibm.com>.
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      d205819e
  9. 21 4月, 2006 1 次提交
    • O
      [PATCH] powerpc: Lower threshold for DART enablement to 1GB · 28897731
      Olof Johansson 提交于
      Turn on the DART already at 1GB. This is needed because of crippled
      devices in some systems, i.e. Airport Extreme cards, only supporting
      30-bit DMA addresses.
      
      Otherwise, users with between 1 and 2GB of memory will need to manually
      enable it with iommu=force, and that's no good.
      
      Some simple performance tests show that there's a slight impact of
      enabling DART, but it's in the 1-3% range (kernel build with disk I/O
      as well as over NFS).
      
      iommu=off can still be used for those who don't want to deal with the
      overhead (and don't need it for any devices).
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      28897731
  10. 28 3月, 2006 3 次提交
  11. 27 3月, 2006 1 次提交
    • A
      [PATCH] powerpc: Allow non zero boot cpuids · 4df20460
      Anton Blanchard 提交于
      We currently have a hack to flip the boot cpu and its secondary thread
      to logical cpuid 0 and 1. This means the logical - physical mapping will
      differ depending on which cpu is boot cpu. This is most apparent on
      kexec, where we might kexec on any cpu and therefore change the mapping
      from boot to boot.
      
      The patch below does a first pass early on to work out the logical cpuid
      of the boot thread. We then fix up some paca structures to match.
      
      Ive also removed the boot_cpuid_phys variable for ppc64, to be
      consistent we use get_hard_smp_processor_id(boot_cpuid) everywhere.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NPaul Mackerras <paulus@samba.org>
      4df20460
  12. 25 2月, 2006 1 次提交
  13. 07 2月, 2006 4 次提交
  14. 13 1月, 2006 2 次提交
  15. 12 1月, 2006 1 次提交
  16. 10 1月, 2006 1 次提交
  17. 09 1月, 2006 5 次提交
  18. 14 11月, 2005 1 次提交
  19. 10 11月, 2005 4 次提交
  20. 08 11月, 2005 1 次提交
  21. 07 11月, 2005 1 次提交
    • B
      [PATCH] ppc64: support 64k pages · 3c726f8d
      Benjamin Herrenschmidt 提交于
      Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel
      base page size to 64K.  The resulting kernel still boots on any
      hardware.  On current machines with 4K pages support only, the kernel
      will maintain 16 "subpages" for each 64K page transparently.
      
      Note that while real 64K capable HW has been tested, the current patch
      will not enable it yet as such hardware is not released yet, and I'm
      still verifying with the firmware architects the proper to get the
      information from the newer hypervisors.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3c726f8d