Add support for the in-kernel GIC emulation.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Handle the exit of a VM, decoding the exit reason from HYP mode
and calling the corresponding handler.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The HYP mode world switch in all its glory.

Implements save/restore of host/guest registers, EL2 trapping,
IPA resolution, and additional services (tlb invalidation).
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Provide EL2 with page tables and stack, and set the vectors
to point to the full blown world-switch code.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Let userspace play with the guest registers.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Provide the reset code for a virtual CPU booted in 64bit mode.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add the support code for CPU specific system registers. Not much
here yet.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Provide 64bit system register handling, modeled after the cp15
handling for ARM.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Implement the injection of a fault (undefined, data abort or
prefetch abort) into a 64bit guest.
Reviewed-by: NChristopher Covington <cov@codeaurora.org>
Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>