Now that we can use clk_hw pointers we don't need to have two
duplicate arrays holding the same mapping of clk index to clk_hw
pointer. Implement a custom clk_hw provider function to map the
OF specifier to the clk_hw instance for it.

Cc: Alex Elder <elder@linaro.org>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().
Signed-off-by: NPurna Chandra Mandal <purna.mandal@microchip.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-meson-gxbb-ao:
  clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()

There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: NWei Yongjun <weiyj.lk@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

sizeof() when applied to a pointer typed expression gives the
size of the pointer, not that of the pointed data.
Signed-off-by: NWei Yongjun <weiyongjun1@huawei.com>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Fixes: f8c11f79 ("clk: meson: Add GXBB AO Clock and Reset controller driver")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add BIMC gdsc data found in MMCC part of msm8996 family of devices.
Signed-off-by: NRajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The SAI_IPG clocks are enabled by the same bits that control SAI_ROOT_CLK
clocks, so represent them as shared clocks.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Introduce imx_clk_gate2_shared2() which is similar to the existing
imx_clk_gate2_shared() and passes CLK_OPS_PARENT_ENABLE flag, which
is useful for i.MX7 shared clocks.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add IMX7D_SDMA_CORE_CLK clock so that SDMA can be functional.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-meson-gxbb-ao:
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings

Adds a Clock and Reset controller driver for the Always-On part
of the Amlogic Meson GXBB SoC.

It exports paired Clocks and Resets lines that will be used by
peripherals in the Always-On subsystem.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add documentations and dt-bindings headers for the AO clock and reset
controller.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.
Signed-off-by: NShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: NShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: NShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Tested-by: NJohn Crispin <blogic@openwrt.org>
Reviewed-by: NMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Remove __init from functions that will be used by init functions
that support probe deferral.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NErin Lo <erin.lo@mediatek.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.

Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The offset of Core Cluster clock control/status register
on cluster group V3 version is different from others, and
should be plus 0x70000.
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: NScott Wood <oss@buserror.net>
Fixes: 9e19ca2f ("clk: qoriq: Add ls2080a support.")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs.
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Cc: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Merge r8a7796 watchdog clk support from Geert Uytterhoeven:

Add all clocks related to the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

* tag 'clk-renesas-for-v4.9-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add watchdog module clock
  clk: renesas: r8a7796: Add watchdog core clocks

Now that we have clk_hw based provider APIs to register clks, we
can get rid of struct clk pointers while registering clks in
these drivers, allowing us to move closer to a clear split of
consumer and provider clk APIs. We also remove some __init
markings in header files as they're useless and we're in the
area.
Tested-by: NJisheng Zhang <jszhang@marvell.com>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NStephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The field "owner" is set by the core.
Thus delete an unneeded initialisation.

Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
Signed-off-by: NMarkus Elfring <elfring@users.sourceforge.net>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We've started getting out of order, fix it.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-qcom-9615:
  dt-bindings: clock: Update bindings for MDM9615 GCC and LCC
  clk: mdm9615: Add support for MDM9615 Clock Controllers
  dt-bindings: Add MDM9615 DT bindings include files for GCC and LCC

Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In order to support the Qualcomm MDM9615 SoC, add support for
the Global and LPASS Clock Controllers.
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* clk-meson-gxbb:
  clk: gxbb: add MMC gate clocks, and expose for DT

Add the SD/eMMC gate clocks and expose them for use by DT.

While at it, also explose FCLK_DIV2 since this is one of the input
clocks to the mux internal to each of the SD/eMMC blocks.
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
Tested-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Maxim Max77620 has one 32KHz clock output and the clock HW
IP used on this PMIC is same as what it is there in the MAX77686.

Add clock driver support for MAX77620 on the MAX77686 driver.

CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Maxim has used the same clock IP on multiple PMICs like MAX77686,
MAX77802, MAX77620. Only differences are the number of clocks
from these PMICs like MAX77686 has 3 clocks output, MAX776802 have
two clock output and MAX77620 has one clock output.

Add clock binding details and DT example for the MAX77620.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.

Define the common DT binding file for the clocks of Maxim PMICs
MAX77686 and MAX77802. For this, remove the separate DT binding
document file for maxim,max77802 and move all information to
maxim,max77686 DT binding document.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: NRob Herring <robh@kernel.org>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The clock IP used on the Maxim PMICs max77686 and max77802 are
same. The configuration of clock register is also same except
the number of clocks.

Part of common code utilisation, there is 3 files for these chips
clock driver, one for common and two files for driver registration.

Combine both drivers into single file and move common code into
same common file reduces the 2 files and make max77686 and max77802
clock driver in single fine. This driver does not depends on the
parent driver structure. The regmap handle is acquired through
regmap APIs for the register access.

This combination of driver helps on adding clock driver for different
Maxim PMICs which has similar clock IP like MAX77620 and MAX20024.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
CC: Krzysztof Kozlowski <k.kozlowski@samsung.com>
CC: Javier Martinez Canillas <javier@dowhile0.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Tested-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This function is only called by builtin code, but we always
exported it and had marked it as __init before commit
e4eda8e0 (clk: remove exported function from __init section,
2013-01-06) removed that marking. Given that it isn't used by
modules, lets unexport it and add back __init.

Cc: Denis Efremov <yefremov.denis@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This function is marked __init, so it can't possibly need to be
exported to modules. Remove the marking.

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Before commit 0861e5b8 (clk: Add clk_hw OF clk providers,
2016-02-05) __of_clk_get_from_provider() would return an error
pointer of the provider's choosing if there was a provider
registered and EPROBE_DEFER otherwise. After that commit, it
would return EPROBE_DEFER regardless of whether or not the
provider returned an error. This is odd and can lead to behavior
where clk consumers keep probe deferring when they should be
seeing some other error.

Let's restore the previous behavior where we only return
EPROBE_DEFER when there isn't a provider in our of_clk_providers
list. Otherwise, return the error from the last provider we find
that matches the node.
Reported-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Fixes: 0861e5b8 ("clk: Add clk_hw OF clk providers")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use the builtin_platform_driver() macro to make the code simpler.
Signed-off-by: NWei Yongjun <weiyj.lk@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

These clocks are the ones which will be used as source for the
peripherals of the Armada 3700 SoC. On this SoC there is two blocks of
clocks: the North bridge one and the South bridge one.

Most of them are gatable. Most of the time their rate are their parent
rated divided by a ratio depending of two registers. Their parent can be
choose between the TBG clocks for most of them.

However, some of them can't choose their parent or directly depend of the
xtal clocks. Other ones do not use exactly the same pattern to find the
ratio between their parent rate and their rate.

For these reason each clock is a composite clock and the operations they
use are different depending of the clock.

According to the datasheet it would be possible to select the parent
clock and the ratio, however currently the driver does not support it.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>