1. 03 3月, 2015 21 次提交
  2. 24 2月, 2015 2 次提交
  3. 23 2月, 2015 5 次提交
  4. 13 2月, 2015 2 次提交
  5. 12 2月, 2015 4 次提交
  6. 11 2月, 2015 4 次提交
  7. 10 2月, 2015 2 次提交
    • S
      drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL · 4ba7d93a
      Shobhit Kumar 提交于
      LP_OUTPUT_HOLD is only in MIPI_PORT_CTRL(PORT_A) even for PORT_C in case
      of dual link. In the dual link implementation, the bit is correctly set
      or unset for hardcoded PORT_A, but for bit update the register base value
      is read by using MIPI_PORT_CTRL(port) in a loop. The second iteration will
      read base value from PORT_C and program for PORT_A. Mostly in case of dual
      link all other bit values should be same, but logically we should read from
      PORT_A. So hardcode to read initial value from PORT_A as well.
      Signed-off-by: NShobhit Kumar <shobhit.kumar@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      4ba7d93a
    • C
      drm/i915: Insert a command barrier on BLT/BSD cache flushes · f0a1fb10
      Chris Wilson 提交于
      This looked like an odd regression from
      
      commit ec5cc0f9
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Thu Jun 12 10:28:55 2014 +0100
      
          drm/i915: Restrict GPU boost to the RCS engine
      
      but in reality it undercovered a much older coherency bug. The issue that
      boosting the GPU frequency on the BCS ring was masking was that we could
      wake the CPU up after completion of a BCS batch and inspect memory prior
      to the write cache being fully evicted. In order to serialise the
      breadcrumb interrupt (and so ensure that the CPU's view of memory is
      coherent) we need to perform a post-sync operation in the MI_FLUSH_DW.
      
      v2: Fix all the MI_FLUSH_DW (bsd plus the duplication in execlists).
      
      Also fix the invalidate_domains mask in gen8_emit_flush() for ring !=
      VCS.
      
      Testcase: gpuX-rcs-gpu-read-after-write
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: stable@vger.kernel.org
      Acked-by: NDaniel Vetter <daniel@ffwll.ch>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      f0a1fb10