1. 31 3月, 2014 1 次提交
  2. 17 2月, 2011 1 次提交
  3. 17 12月, 2008 1 次提交
  4. 07 12月, 2007 1 次提交
    • H
      [AVR32] Fix copy_to_user_page() breakage · 68ca3e53
      Haavard Skinnemoen 提交于
      The current implementation of copy_to_user_page() gives "vaddr" to the
      cache instruction when trying to sync the icache with the dcache. If
      vaddr does not exist in the TLB, the CPU will silently abort the
      operation, which may result in the caches staying out of sync.
      
      To fix this, pass the "dst" parameter to flush_icache_range() instead
      -- we know this is valid because we just wrote to it.
      Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
      68ca3e53
  5. 23 6月, 2007 1 次提交
    • H
      [AVR32] Fix bug in invalidate_dcache_region() · ab61f7d2
      Haavard Skinnemoen 提交于
      If (start + size) is not cacheline aligned and (start & mask) > (end &
      mask), the last but one cacheline won't be invalidated as it should.
      Fix this by rounding `end' down to the nearest cacheline boundary if
      it gets adjusted due to misalignment.
      
      Also flush the write buffer unconditionally -- if the dcache wrote
      back a line just before we invalidated it, the dirty data may be
      sitting in the write buffer waiting to corrupt our buffer later.
      Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>
      ab61f7d2
  6. 07 3月, 2007 1 次提交
  7. 09 2月, 2007 1 次提交
  8. 26 9月, 2006 1 次提交