This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'omap-for-v4.3/dt-pt4-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt

Fix up bogus RTC compatible change for am4372 and add missing
DPLL for am4372 cpsw Ethernet driver. Also add ARM global and
local timers for am4372.

* tag 'omap-for-v4.3/dt-pt4-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  arm: boot: dts: am4372: add ARM timers and SCU nodes
  ARM: dts: AM4372: Add the am4372-rtc compatible string
  ARM: dts: am4372: Set the default clock rate for dpll_clksel_mac_clk clock
  ARM: dts: AM437X: add dpll_clksel_mac_clk node
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Fourth Round of Renesas ARM Based SoC DT Updates for v4.3

* Enable Clock Domain support of the Clock Pulse Generator (CPG)
  Module Stop (MSTP) Clocks driver.

* tag 'renesas-dt4-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7791 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7790 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7779 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r8a7778 dtsi: Add CPG/MSTP Clock Domain
  ARM: shmobile: r7s72100 dtsi: Add CPG/MSTP Clock Domain
  clk: shmobile: rz: Add CPG/MSTP Clock Domain support
  clk: shmobile: rcar-gen2: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7779: Add CPG/MSTP Clock Domain support
  clk: shmobile: r8a7778: Add CPG/MSTP Clock Domain support
  clk: shmobile: Add CPG/MSTP Clock Domain support
Signed-off-by: NOlof Johansson <olof@lixom.net>

The sp810 clk driver is calling the clk consumer APIs from
clk_prepare ops to change the parent to a 1 MHz fixed rate clock
for each of the clocks that the driver provides. Use
assigned-clock-parents for this instead of doing it in the driver
to avoid using the consumer API in provider code. This also
allows us to remove the usage of clk provider APIs that take a
struct clk as an argument from the sp810 driver.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Tested-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The i.MX device tree updates for 4.3:
 - Add audio and eTSEC device support and update dspi node for LS1021A.
 - Add initial i.MX6UL and imx6ul-14x14-evk board support, and enable
   a bunch of device support for i.MX6UL, including RTC, power key, USB,
   QSPI, and dual FEC.
 - Enable HDMI and LVDS dual display support for a few imx6qdl boards.
 - Support of imx6sl-warp board rev1.12, the version which will be
   publicly available for the customers.
 - A few i.MX7D device additions, watchdog, cortex-a7 coresight
   components, RTC, power key, power off.
 - Some Vybrid updates: add device support for I2C, QSPI, eSDHC etc.,
   update ADC node, and define stdout-path property.
 - A few random updates for i.MX27 and i.MX53 devices.

* tag 'imx-dt-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (44 commits)
  ARM: dts: imx6ul: add snvs power key support
  ARM: dts: imx6ul: add RTC support
  ARM: dts: imx6ul: enable GPC as extended interrupt controller
  ARM: dts: imx6sx: correct property name for wakeup source
  ARM: dts: add property for maximum ADC clock frequencies
  ARM: dts: imx7d: enable snvs rtc, onoffkey and power off
  ARM: dts: imx6ul-14x14-evk: add fec1 and fec2 support
  ARM: dts: imx: add fec1 and fec2 nodes for SOC i.MX6UL
  ARM: dts: imx27: add support of internal rtc
  ARM: dts: vf-colibri: define stdout-path property
  ARM: dts: ls1021a: Enable the eTSEC ports on QDS and TWR
  ARM: dts: ls1021a: Add the eTSEC controller nodes
  ARM: dts: imx6ul: add qspi support
  ARM: dts: imx6ul: fix low case define in imx6ul-pinfunc.h
  ARM: dts: imx6ul: add usb host and function support
  ARM: dts: vfxxx: Add io-channel-cells property for ADC node
  ARM: dts: ls1021a: Add dts nodes for audio on LS1021A
  ARM: imx6qdl-sabreauto.dtsi: enable USB support
  ARM: dts: imx: update snvs to use syscon access register
  ARM: dts: imx: add imx6ul and imx6ul evk board support
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'rpi-dt-for-armsoc-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi into next/dt

 - New Firmware node and accompanying binding document

* tag 'rpi-dt-for-armsoc-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi:
  dt/bindings: Add binding for the Raspberry Pi firmware driver
  ARM: bcm2835: Add the firmware driver information to the RPi DT
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt

SoCFPGA DTS updates for v4.3, take 2
- Add DTS property "altr,modrst-offset" for reset driver to
  use
- Add updated reset defines for the reset driver
- Add reset property for EMACs on Arria10

* tag 'socfpga_dts_for_v4.3_part_2' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
  ARM: socfpga: dts: Add resets for EMACs on Arria10
  ARM: socfpga: dts: add "altr,modrst-offset" property
  dt-bindings: Add reset manager offsets for Arria10
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'v4.3-rockchip32-dts2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Some more devicetree changes, including usbphy support for the
Cortex-A9 SoCs and actually enabling usb on the rk3066-marsboard,
Two more veyron-devices - namely Speedy and Minnie and a fix for
the tsadc.
One slightly more interesting fix is the blocking of the last
16MB of memory on 4GB rk3288 devices. The rk3288 cannot use this
area for dma operations, so things like the mmc or usb controllers
regularly fail when trying to read data. This solution mimicks the
solution from the ChromeOS kernel, who also do not seem to have
found a better solution yet. Here it only moves to the devicetree.
As this issue is also present on the arm64 rk3368, any future
better solution to this problem would need to describe this in
the devicetree as well and could then remove this block.

* tag 'v4.3-rockchip32-dts2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: add veyron-minnie board
  ARM: dts: rockchip: reserve unusable memory region on rk3288
  ARM: dts: rockchip: enable usb controller on marsboard
  ARM: dts: rockchip: add usb phys to Cortex-A9 socs
  ARM: dts: rockchip: set correct dwc2 params for cortex-a9 socs
  ARM: dts: rockchip: Add veyron-speedy board
  ARM: dts: rockchip: Use correct dts properties for tsadc node on veyron
Signed-off-by: NOlof Johansson <olof@lixom.net>

mvebu dt changes for v4.3 (part #3)

- device tree part of the Dove PMU series
- converting a new orion5x based platform to dt: Linkstation Mini

* tag 'mvebu-dt-4.3-3' of git://git.infradead.org/linux-mvebu:
  ARM: dts: Convert Linkstation Mini to Device Tree
  ARM: dt: dove: add GPU power domain description
  ARM: dt: dove: add video decoder power domain description
  ARM: dt: dove: wire up RTC interrupt
  ARM: dt: Add PMU node, making PMU child devices childs of this node
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'at91-ab-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/dt

Second batch of DT changes for 4.3:
- Add the slow clock to the nodes that will use it
- Add hlcd to the at91sam9x5 and at91sam9n12
- Add touchscreen and touch button support to the at91sam9x5ek

* tag 'at91-ab-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux: (22 commits)
  ARM: at91/dt: sama5d2: use slow clock where necessary
  ARM: at91/dt: at91sam9x5dm: add QT1070 touch button controller
  ARM: at91/dt: at91sam9x5dm: add support for the touschscreen
  ARM: at91/dt: add drm support for at91sam9n12ek
  ARM: at91/dt: enable lcd support for at91sam9x5 SoCs
  ARM: at91/dt: add at91sam9x5-ek Display Module dtsi
  ARM: at91/dt: include lcd dtsi in at91sam9x5 dtsis
  ARM: at91/dt: define hlcdc node in at91sam9x5_lcd.dtsi
  ARM: at91/dt: sama5d4: use slow clock where necessary
  ARM: at91/dt: sama5d3: use slow clock where necessary
  ARM: at91/dt: at91sam9x5: use slow clock where necessary
  ARM: at91/dt: at91sam9rl: use slow clock where necessary
  ARM: at91/dt: at91sam9n12: use slow clock where necessary
  ARM: at91/dt: at91sam9g45: use slow clock where necessary
  ARM: at91/dt: at91sam9263: use slow clock where necessary
  ARM: at91/dt: at91sam9261: use slow clock where necessary
  ARM: at91/dt: at91sam9260: use slow clock where necessary
  ARM: at91/dt: at91rm9200: use slow clock where necessary
  Documentation: dt: rtc: at91rm9200: add clocks property
  Documentation: watchdog: at91sam9_wdt: add clocks property
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

AM437x devices sport SCU, TWD and Global timers,
let's add them to DTS so they have a chance to
probe and be used by Linux.
Signed-off-by: NFelipe Balbi <balbi@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

am4372-rtc string was already part of dts, introduced to identify
the rtc specific to am4372 family of SoCs. It was removed in one of the
previous patches. Adding back the same with appropriate documentation.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  Notable
exceptions are the "display" and "sound" nodes, which represent multiple
SoC devices, each having their own MSTP clocks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.  A notable
exception is the "sound" node, which represents multiple SoC devices,
each having their own MSTP clocks.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add an appropriate "#power-domain-cells" property to the cpg_clocks
device node, to create the CPG/MSTP Clock Domain.

Add "power-domains" properties to all device nodes for devices that are
part of the CPG/MSTP Clock Domain and can be power-managed through an
MSTP clock.  This applies to most on-SoC devices, which have a
one-to-one mapping from SoC device to DT device node.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Clock Domain support to the RZ Clock Pulse Generator (CPG) driver
using the generic PM Domain.  This allows to power-manage the module
clocks of SoC devices that are part of the CPG/MSTP Clock Domain using
Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Clock Domain support to the R-Car Gen2 Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Clock Domain support to the R-Car H1 Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.

Also update the reg property in the DT binding doc example to match the
actual dtsi, which uses #address-cells and #size-cells == 1, not 2.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Clock Domain support to the R-Car M1A Clock Pulse Generator (CPG)
driver using the generic PM Domain.  This allows to power-manage the
module clocks of SoC devices that are part of the CPG/MSTP Clock Domain
using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a proper
"power-domains" property.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

Add Clock Domain support to the Clock Pulse Generator (CPG) Module Stop
(MSTP) Clocks driver using the generic PM Domain.  This allows to
power-manage the module clocks of SoC devices that are part of the
CPG/MSTP Clock Domain using Runtime PM, or for system suspend/resume.

SoC devices that are part of the CPG/MSTP Clock Domain and can be
power-managed through an MSTP clock should be tagged in DT with a
proper "power-domains" property.

The CPG/MSTP Clock Domain code will scan such devices for clocks that
are suitable for power-managing the device, by looking for a clock that
is compatible with "renesas,cpg-mstp-clocks".
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Reviewed-by: NUlf Hansson <ulf.hansson@linaro.org>
Reviewed-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>

This driver will provide support for calls into the firmware that will
be used by other drivers like cpufreq and vc4.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Add i.MX6UL SNVS power key support.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add RTC support for i.MX6UL.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Enable GPC as extended interrupt controller of
GIC, as GPC needs to manage wakeup source for
low power modes.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Commit(def56bba input: snvs_pwrkey: use "wakeup-source"
as deivce tree property name) replaces the property name
of "wakeup" with "wakeup-source", update this change
in i.MX6SX dtsi accordingly.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The ADC clock frequency is limited depending on modes used. Add
device tree property which allow to set the mode used and the
maximum frequency ratings for the instance. These allows to
set the ADC clock to a frequency which is within specification
according to the actual mode used.
Acked-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Change SNVS rtc to syscon interface.
Enable onoff key and power off function.
Signed-off-by: NFrank Li <Frank.Li@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add ethernet fec1 and fec2 support for i.MX6ul 14x14 evk board.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

SOC i.MX6UL has two ethernet MACs, add fec1 and fec2 support for i.MX6UL.
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add support of internal rtc on imx27.
Signed-off-by: NPhilippe Reynes <tremyfr@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Define Vybrid's UART0, connected to the Colibri pinout UART_A, as
standard output.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

This enables the available eTSEC ethernet ports for the
ls1021aqds and ls1021atwr boards.
For the QDS, SGMII connections (via riser cards) are assumed
for the eTSEC0 and eTSEC1 ports as default configuration.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

Add basic support for all the eTSEC controllers on the
ls1021a SoC.  Second interrupt group register blocks
and their corresponding Rx/Tx/Err interrupt sources are
included as well for each eTSEC node.
Signed-off-by: NAlison Wang <alison.wang@freescale.com>
Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>