1. 29 7月, 2008 1 次提交
  2. 28 7月, 2008 1 次提交
  3. 28 4月, 2008 1 次提交
    • N
      mm: introduce pte_special pte bit · 7e675137
      Nick Piggin 提交于
      s390 for one, cannot implement VM_MIXEDMAP with pfn_valid, due to their memory
      model (which is more dynamic than most).  Instead, they had proposed to
      implement it with an additional path through vm_normal_page(), using a bit in
      the pte to determine whether or not the page should be refcounted:
      
      vm_normal_page()
      {
      	...
              if (unlikely(vma->vm_flags & (VM_PFNMAP|VM_MIXEDMAP))) {
                      if (vma->vm_flags & VM_MIXEDMAP) {
      #ifdef s390
      			if (!mixedmap_refcount_pte(pte))
      				return NULL;
      #else
                              if (!pfn_valid(pfn))
                                      return NULL;
      #endif
                              goto out;
                      }
      	...
      }
      
      This is fine, however if we are allowed to use a bit in the pte to determine
      refcountedness, we can use that to _completely_ replace all the vma based
      schemes.  So instead of adding more cases to the already complex vma-based
      scheme, we can have a clearly seperate and simple pte-based scheme (and get
      slightly better code generation in the process):
      
      vm_normal_page()
      {
      #ifdef s390
      	if (!mixedmap_refcount_pte(pte))
      		return NULL;
      	return pte_page(pte);
      #else
      	...
      #endif
      }
      
      And finally, we may rather make this concept usable by any architecture rather
      than making it s390 only, so implement a new type of pte state for this.
      Unfortunately the old vma based code must stay, because some architectures may
      not be able to spare pte bits.  This makes vm_normal_page a little bit more
      ugly than we would like, but the 2 cases are clearly seperate.
      
      So introduce a pte_special pte state, and use it in mm/memory.c.  It is
      currently a noop for all architectures, so this doesn't actually result in any
      compiled code changes to mm/memory.o.
      
      BTW:
      I haven't put vm_normal_page() into arch code as-per an earlier suggestion.
      The reason is that, regardless of where vm_normal_page is actually
      implemented, the *abstraction* is still exactly the same. Also, while it
      depends on whether the architecture has pte_special or not, that is the
      only two possible cases, and it really isn't an arch specific function --
      the role of the arch code should be to provide primitive functions and
      accessors with which to build the core code; pte_special does that. We do
      not want architectures to know or care about vm_normal_page itself, and
      we definitely don't want them being able to invent something new there
      out of sight of mm/ code. If we made vm_normal_page an arch function, then
      we have to make vm_insert_mixed (next patch) an arch function too. So I
      don't think moving it to arch code fundamentally improves any abstractions,
      while it does practically make the code more difficult to follow, for both
      mm and arch developers, and easier to misuse.
      
      [akpm@linux-foundation.org: build fix]
      Signed-off-by: NNick Piggin <npiggin@suse.de>
      Acked-by: NCarsten Otte <cotte@de.ibm.com>
      Cc: Jared Hulbert <jaredeh@gmail.com>
      Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
      Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      7e675137
  4. 28 1月, 2008 5 次提交
  5. 07 11月, 2007 1 次提交
  6. 30 10月, 2007 1 次提交
    • P
      sh: Correct pte_page() breakage. · afca0357
      Paul Mundt 提交于
      As noted by David:
      
      pte_page() is a macro defined as follows;
      
          include/asm-sh/pgtable.h
          #define pte_page(x)    phys_to_page(pte_val(x)&PTE_PHYS_MASK)
      
          include/asm-sh/page.h
          #define phys_to_page(phys)    (pfn_to_page(phys >> PAGE_SHIFT))
      
      So as you can see the phys_to_page() macro doesn't wrap the 'phys'
      parameter in parentheses so we end up with;
      
          pte_val(x)&PTE_PHYS_MASK >> PAGE_SHIFT
      
      Which is not what we wanted as '>>' has a higher precedence than bitwise
      AND. I dug into the git repository and I believe this bug was added with
      this commit (104b8dea);
      
      2006-03-27 KAMEZAWA Hiroyuki [PATCH] unify pfn_to_page: sh pfn_to_page
      
      -#define phys_to_page(phys)     (mem_map + (((phys)-__MEMORY_START) >>
      PAGE_SHIFT))
      -#define page_to_phys(page)     (((page - mem_map) << PAGE_SHIFT) +
      __MEMORY_START)
      +#define phys_to_page(phys)     (pfn_to_page(phys >> PAGE_SHIFT))
      +#define page_to_phys(page)     (page_to_pfn(page) << PAGE_SHIFT)
      Reported-by: NDavid ADDISON <david.addison@st.com>
      Reported-by: NKAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      afca0357
  7. 21 9月, 2007 2 次提交
    • P
      sh: Fix up extended mode TLB for SH-X2+ cores. · d04a0f79
      Paul Mundt 提交于
      The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
      correspondingly, the PGD also has to be 64-bits, so fix that up.
      
      The kernel and user permission bits really are decoupled in early
      cuts of the silicon, which means that we also have to set corresponding
      kernel permissions on user pages or we end up with user pages that the
      kernel simply can't touch (!).
      
      Finally, with those things corrected, really enable MMUCR.ME and
      correct the PTEA value (this simply needs to be the upper 32-bits
      of the PTE, with the size and protection bit encoding).
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      d04a0f79
    • P
      sh: Support explicit L1 cache disabling. · e7bd34a1
      Paul Mundt 提交于
      This reworks the cache mode configuration in Kconfig, and allows for
      explicit selection of write-back/write-through/off configurations.
      All of the cache flushing routines are optimized away for the off
      case.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      e7bd34a1
  8. 25 7月, 2007 1 次提交
  9. 17 7月, 2007 1 次提交
  10. 09 5月, 2007 1 次提交
  11. 05 3月, 2007 1 次提交
  12. 14 2月, 2007 1 次提交
  13. 13 2月, 2007 2 次提交
    • P
      sh: Lazy dcache writeback optimizations. · 26b7a78c
      Paul Mundt 提交于
      This converts the lazy dcache handling to the model described in
      Documentation/cachetlb.txt and drops the ptep_get_and_clear() hacks
      used for the aliasing dcaches on SH-4 and SH7705 in 32kB mode. As a
      bonus, this slightly cuts down on the cache flushing frequency.
      
      With that and the PTEA handling out of the way, the update_mmu_cache()
      implementations can be consolidated, and we no longer have to worry
      about which configuration the cache is in for the SH7705 case.
      
      And finally, explicitly disable the lazy writeback on SMP (SH-4A).
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      26b7a78c
    • P
      sh: More tidying for large base pages. · 7a847f81
      Paul Mundt 提交于
      There were a few more things that needed fixing up, namely THREAD_SIZE
      and the TLB miss handler where certain PTRS_PER_PGD == PTRS_PER_PTE
      assumptions were being made.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      7a847f81
  14. 12 12月, 2006 2 次提交
  15. 06 12月, 2006 5 次提交
    • P
      sh: Fixup pte_mkhuge() build failure. · 5b67954e
      Paul Mundt 提交于
      When hugetlbpage support isn't enabled, this can be bogus.
      Wrap it back in _PAGE_FLAGS_HARD to avoid changes to the
      base PTE when not aiming for larger sizes.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      5b67954e
    • P
      sh: Fixup various PAGE_SIZE == 4096 assumptions. · 510c72ad
      Paul Mundt 提交于
      There were a number of places that made evil PAGE_SIZE == 4k
      assumptions that ended up breaking when trying to play with
      8k and 64k page sizes, this fixes those up.
      
      The most significant change is the way we load THREAD_SIZE,
      previously this was done via:
      
      	mov	#(THREAD_SIZE >> 8), reg
      	shll8	reg
      
      to avoid a memory access and allow the immediate load. With
      a 64k PAGE_SIZE, we're out of range for the immediate load
      size without resorting to special instructions available in
      later ISAs (movi20s and so on). The "workaround" for this is
      to bump up the shift to 10 and insert a shll2, which gives a
      bit more flexibility while still being much cheaper than a
      memory access.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      510c72ad
    • S
      sh: TLB miss fast-path optimizations. · 9b3a53ab
      Stuart Menefy 提交于
      Handle simple TLB miss faults which can be resolved completely
      from the page table in assembler.
      Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      9b3a53ab
    • S
      sh: pmd rework. · 99a596f9
      Stuart Menefy 提交于
      Remove extra bits from the pmd structure and store a kernel logical
      address rather than a physical address. This allows it to be directly
      dereferenced. Another piece of wierdness inherited from x86.
      Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      99a596f9
    • P
      sh: Preliminary support for SH-X2 MMU. · 21440cf0
      Paul Mundt 提交于
      This adds some preliminary support for the SH-X2 MMU, used by
      newer SH-4A parts (particularly SH7785).
      
      This MMU implements a 'compat' mode with SH-X MMUs and an
      'extended' mode for SH-X2 extended features. Extended features
      include additional page sizes (8kB, 4MB, 64MB), as well as the
      addition of page execute permissions.
      
      The extended mode attributes are placed in a second data array,
      which requires us to switch to 64-bit PTEs when in X2 mode.
      
      With the addition of the exec perms, we also overhaul the mmap
      prots somewhat, now that it's possible to handle them more
      intelligently.
      Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
      21440cf0
  16. 27 9月, 2006 3 次提交
  17. 26 9月, 2006 1 次提交
    • D
      [PATCH] Standardize pxx_page macros · 46a82b2d
      Dave McCracken 提交于
      One of the changes necessary for shared page tables is to standardize the
      pxx_page macros.  pte_page and pmd_page have always returned the struct
      page associated with their entry, while pte_page_kernel and pmd_page_kernel
      have returned the kernel virtual address.  pud_page and pgd_page, on the
      other hand, return the kernel virtual address.
      
      Shared page tables needs pud_page and pgd_page to return the actual page
      structures.  There are very few actual users of these functions, so it is
      simple to standardize their usage.
      
      Since this is basic cleanup, I am submitting these changes as a standalone
      patch.  Per Hugh Dickins' comments about it, I am also changing the
      pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning.
      Signed-off-by: NDave McCracken <dmccr@us.ibm.com>
      Cc: Hugh Dickins <hugh@veritas.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      46a82b2d
  18. 26 4月, 2006 1 次提交
  19. 07 11月, 2005 2 次提交
  20. 31 10月, 2005 1 次提交
    • T
      [PATCH] vm: remove unused/broken page_pte[_prot] macros · 1426d7a8
      Tejun Heo 提交于
      This patch removes page_pte_prot and page_pte macros from all
      architectures.  Some architectures define both, some only page_pte (broken)
      and others none.  These macros are not used anywhere.
      
      page_pte_prot(page, prot) is identical to mk_pte(page, prot) and
      page_pte(page) is identical to page_pte_prot(page, __pgprot(0)).
      
      * The following architectures define both page_pte_prot and page_pte
      
        arm, arm26, ia64, sh64, sparc, sparc64
      
      * The following architectures define only page_pte (broken)
      
        frv, i386, m32r, mips, sh, x86-64
      
      * All other architectures define neither
      Signed-off-by: NTejun Heo <htejun@gmail.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      1426d7a8
  21. 13 9月, 2005 1 次提交
  22. 22 6月, 2005 1 次提交
    • D
      [PATCH] Hugepage consolidation · 63551ae0
      David Gibson 提交于
      A lot of the code in arch/*/mm/hugetlbpage.c is quite similar.  This patch
      attempts to consolidate a lot of the code across the arch's, putting the
      combined version in mm/hugetlb.c.  There are a couple of uglyish hacks in
      order to covert all the hugepage archs, but the result is a very large
      reduction in the total amount of code.  It also means things like hugepage
      lazy allocation could be implemented in one place, instead of six.
      
      Tested, at least a little, on ppc64, i386 and x86_64.
      
      Notes:
      	- this patch changes the meaning of set_huge_pte() to be more
      	  analagous to set_pte()
      	- does SH4 need s special huge_ptep_get_and_clear()??
      Acked-by: NWilliam Lee Irwin <wli@holomorphy.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      63551ae0
  23. 20 4月, 2005 1 次提交
  24. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4