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  1. 21 2月, 2011 10 次提交
  3. 20 2月, 2011 1 次提交
    • S
      ARM: tegra: Prevent requeuing in-progress DMA requests · 499ef7a5
      由 Stephen Warren 提交于 
      If a request already in the queue is passed to tegra_dma_enqueue_req,
tegra_dma_req.node->{next,prev} will end up pointing to itself instead
of at tegra_dma_channel.list, which is the way a the end-of-list
should be set up. When the DMA request completes and is list_del'd,
the list head will still point at it, yet the node's next/prev will
contain the list poison values. When the next DMA request completes,
a kernel panic will occur when those poison values are dereferenced.

This makes the DMA driver more robust in the face of buggy clients.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>
      499ef7a5
  5. 11 2月, 2011 6 次提交
    • M
      ARM: tegra: add TrimSlice board · cca414b2
      由 Mike Rapoport 提交于 
      Add basic support for CompuLab TrimSlice platform
Signed-off-by: NMike Rapoport <mike@compulab.co.il>
Signed-off-by: NColin Cross <ccross@android.com>
      cca414b2
    • C
      ARM: tegra: Use writel_relaxed in tegra_init_cache · 535371c3
      由 Colin Cross 提交于 
      Signed-off-by: NColin Cross <ccross@android.com>
      535371c3
    • C
      ARM: tegra: dma: Fix critical data corruption bugs · 5789fee9
      由 Colin Cross 提交于 
      Sometimes, due to high interrupt latency in the continuous mode
of DMA transfer, the half buffer complete interrupt is handled
after DMA has transferred the full buffer.  When this is detected,
stop DMA immediately and restart with the next buffer if the next
buffer is ready.

originally fixed by Victor(Weiguo) Pan <wpan@nvidia.com>

In place of using the simple spin_lock()/spi_unlock() in the
interrupt thread, using the spin_lock_irqsave() and
spin_unlock_irqrestore(). The lock is shared between the normal
process context and interrupt context.

originally fixed by Laxman Dewangan (ldewangan@nvidia.com)

The use of shadow registers caused memory corruption at physical
address 0 because the enable bit was not shadowed, and assuming it
needed to be set would enable an unconfigured dma block.  Most of the
register accesses don't need to know the previous state of the
registers, and the few places that do need to modify only a few bits
in the registers are the same ones that were sometimes incorrectly
setting the enable bit.  This patch convert tegra_dma_update_hardware
to set the entire register, and the other users to read-modify-write,
and drops the shadow registers completely.

Also fixes missing locking in tegra_dma_allocate_channel
Signed-off-by: NColin Cross <ccross@android.com>
      5789fee9
    • C
      ARM: tegra: Allow overriding arch_reset · 699fe145
      由 Colin Cross 提交于 
      Signed-off-by: NColin Cross <ccross@android.com>
      699fe145
    • C
      ARM: tegra: cpufreq: Disable cpufreq during suspend · 1eb2ecf1
      由 Colin Cross 提交于 
      On Tegra, calling clk_set_rate on the CPU clock may call into the
regulator API.  If the regulator driver that controls the CPU
voltage rail has been suspended, this can lead to attempted
communication with a hardware block that has already been turned
off.

Adds a SUSPEND_PREPARE notification hook to drop the frequency to
the lowest possible during suspend.

Also adds 216MHz (off of PLLP) as the lowest CPU frequency, which
allows PLLX to be turned off.
Signed-off-by: NColin Cross <ccross@android.com>
      1eb2ecf1
    • G
      ARM: tegra: iomap: Add missing devices · 537f5af0
      由 Gary King 提交于 
      Adds gart, hdmi, avp, host1x, and pwm controllers to mach/iomap.h
Signed-off-by: NGary King <gking@nvidia.com>
Signed-off-by: NColin Cross <ccross@android.com>
      537f5af0
  7. 10 2月, 2011 9 次提交
  9. 01 2月, 2011 1 次提交
  11. 27 1月, 2011 3 次提交
  13. 26 1月, 2011 1 次提交
  15. 21 1月, 2011 1 次提交
  17. 14 1月, 2011 2 次提交
  19. 09 1月, 2011 1 次提交
  21. 23 12月, 2010 3 次提交
  23. 20 12月, 2010 2 次提交