1. 27 6月, 2006 6 次提交
  2. 26 6月, 2006 2 次提交
  3. 23 6月, 2006 4 次提交
  4. 09 6月, 2006 1 次提交
    • A
      [PATCH] Fix HPET operation on 64-bit NVIDIA platforms · a2ef3a50
      Andy Currid 提交于
      From: "Andy Currid" <ACurrid@nvidia.com>
      
      This patch fixes a kernel panic during boot that occurs on NVIDIA platforms
      that have HPET enabled.
      
      When HPET is enabled, the standard timer IRQ is routed to IOAPIC pin 2 and is
      advertised as such in the ACPI APIC table - but an earlier workaround in the
      kernel was ignoring this override.  The fix is to honor timer IRQ overrides
      from ACPI when HPET is detected on an NVIDIA platform.
      Signed-off-by: NAndy Currid <acurrid@nvidia.com>
      Cc: "Brown, Len" <len.brown@intel.com>
      Cc: "Yu, Luming" <luming.yu@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      a2ef3a50
  5. 31 5月, 2006 5 次提交
  6. 22 5月, 2006 1 次提交
  7. 16 5月, 2006 2 次提交
  8. 09 5月, 2006 5 次提交
    • A
      [PATCH] x86_64: Avoid EBDA area in early boot allocator · ac71d12c
      Andi Kleen 提交于
      Based on analysis&patch from Robert Hentosch
      
      Observed on a Dell PE6850 with 16GB
      
      The problem occurs very early on, when the kernel allocates space for the
      temporary memory map called bootmap. The bootmap overlaps the EBDA region.
      EBDA region is not historically reserved in the e820 mapping. When the
      bootmap is freed it marks the EBDA region as usable.
      
      If you notice in setup.c there is already code to work around the EBDA
      in reserve_ebda_region(), this check however occurs after the bootmap
      is allocated and doesn't prevent the bootmap from using this range.
      
      AK: I redid the original patch. Thanks also to Jan Beulich for
      spotting some mistakes.
      
      Cc: Robert_Hentosch@dell.com
      Cc: jbeulich@novell.com
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      ac71d12c
    • C
      [PATCH] x86_64: add nmi_exit to die_nmi · 8b1ffe95
      Corey Minyard 提交于
      Playing with NMI watchdog on x86_64, I discovered that it didn't
      do what I expected.  It always panic-ed, even when it didn't
      happen from interrupt context.  This patch solves that
      problem for me.  Also, in this case, do_exit() will be called
      with interrupts disabled, I believe.  Would it be wise to also
      call local_irq_enable() after nmi_exit()?
      [Yes I added it -AK]
      
      Currently, on x86_64, any NMI watchdog timeout will cause a panic
      because the irq count will always be set to be in an interrupt
      when do_exit() is called from die_nmi().  If we add nmi_exit() to
      the die_nmi() call (since the nmi will never exit "normally")
      it seems to solve this problem.  The following small program
      can be used to trigger the NMI watchdog to reproduce this:
        main ()
        {
              iopl(3);
              for (;;) asm("cli");
        }
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      8b1ffe95
    • C
      [PATCH] x86_64: fix die_lock nesting · cdc60a4c
      Corey Minyard 提交于
      I noticed this when poking around in this area.
      
      The oops_begin() function in x86_64 would only conditionally claim
      the die_lock if the call is nested, but oops_end() would always
      release the spinlock. This patch adds a nest count for the die lock
      so that the release of the lock is only done on the final oops_end().
      Signed-off-by: NCorey Minyard <minyard@acm.org>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      cdc60a4c
    • A
      [PATCH] x86_64: Check for too many northbridges in IOMMU code · 5192d84e
      Andi Kleen 提交于
      The IOMMU code can only deal with 8 northbridges. Error out when
      more are found.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      5192d84e
    • K
      [PATCH] x86_64: avoid IRQ0 ioapic pin collision · e0c1e9bf
      Kimball Murray 提交于
      The patch addresses a problem with ACPI SCI interrupt entry, which gets
      re-used, and the IRQ is assigned to another unrelated device.  The patch
      corrects the code such that SCI IRQ is skipped and duplicate entry is
      avoided.  Second issue came up with VIA chipset, the problem was caused by
      original patch assigning IRQs starting 16 and up.  The VIA chipset uses
      4-bit IRQ register for internal interrupt routing, and therefore cannot
      handle IRQ numbers assigned to its devices.  The patch corrects this
      problem by allowing PCI IRQs below 16.
      
      Cc: len.brown@intel.com
      
      Signed-off by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e0c1e9bf
  9. 02 5月, 2006 1 次提交
    • M
      [PATCH] x86_64: make PC Speaker driver work · 160bd18e
      Mikael Pettersson 提交于
      The PC Speaker driver's ->probe() routine doesn't even get called in the
      64-bit kernels.  The reason for that is that the arch code apparently has
      to explictly add a "pcspkr" platform device in order for the driver core to
      call the ->probe() routine.  arch/i386/kernel/setup.c unconditionally adds
      a "pcspkr" device, but the x86_64 kernel has no code at all related to the
      PC Speaker.
      
      The patch below copies the relevant code from i386 to x86_64, which makes
      the PC Speaker work for me on x86_64.
      
      Cc: Dmitry Torokhov <dtor_core@ameritech.net>
      Acked-by: NAndi Kleen <ak@muc.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      160bd18e
  10. 01 5月, 2006 1 次提交
  11. 26 4月, 2006 1 次提交
  12. 23 4月, 2006 1 次提交
  13. 20 4月, 2006 2 次提交
    • A
      [PATCH] i386/x86-64: Fix x87 information leak between processes · 18bd057b
      Andi Kleen 提交于
      AMD K7/K8 CPUs only save/restore the FOP/FIP/FDP x87 registers in FXSAVE
      when an exception is pending.  This means the value leak through
      context switches and allow processes to observe some x87 instruction
      state of other processes.
      
      This was actually documented by AMD, but nobody recognized it as
      being different from Intel before.
      
      The fix first adds an optimization: instead of unconditionally
      calling FNCLEX after each FXSAVE test if ES is pending and skip
      it when not needed. Then do a x87 load from a kernel variable to
      clear FOP/FIP/FDP.
      
      This means other processes always will only see a constant value
      defined by the kernel in their FP state.
      
      I took some pain to make sure to chose a variable that's already
      in L1 during context switch to make the overhead of this low.
      
      Also alternative() is used to patch away the new code on CPUs
      who don't need it.
      
      Patch for both i386/x86-64.
      
      The problem was discovered originally by Jan Beulich. Richard
      Brunner provided the basic code for the workarounds, with contribution
      from Jan.
      
      This is CVE-2006-1056
      
      Cc: richard.brunner@amd.com
      Cc: jbeulich@novell.com
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      18bd057b
    • P
      [PATCH] Switch Kprobes inline functions to __kprobes for x86_64 · 3b60211c
      Prasanna S Panchamukhi 提交于
      Andrew Morton pointed out that compiler might not inline the functions
      marked for inline in kprobes.  There-by allowing the insertion of probes
      on these kprobes routines, which might cause recursion.
      
      This patch removes all such inline and adds them to kprobes section
      there by disallowing probes on all such routines.  Some of the routines
      can even still be inlined, since these routines gets executed after the
      kprobes had done necessay setup for reentrancy.
      Signed-off-by: NPrasanna S Panchamukhi <prasanna@in.ibm.com>
      Cc: Andi Kleen <ak@muc.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3b60211c
  14. 19 4月, 2006 1 次提交
  15. 15 4月, 2006 1 次提交
  16. 11 4月, 2006 2 次提交
  17. 10 4月, 2006 4 次提交
    • J
      [PATCH] x86_64: Plug GS leak in arch_prctl() · 97c2803c
      John Blackwood 提交于
      In linux-2.6.16, we have noticed a problem where the gs base value
      returned from an arch_prtcl(ARCH_GET_GS, ...) call will be incorrect if:
      
         - the current/calling task has NOT set its own gs base yet to a
           non-zero value,
      
         - some other task that ran on the same processor previously set their
           own gs base to a non-zero value.
      
      In this situation, the ARCH_GET_GS code will read and return the
      MSR_KERNEL_GS_BASE msr register.
      
      However, since the __switch_to() code does NOT load/zero the
      MSR_KERNEL_GS_BASE register when the task that is switched IN has a zero
      next->gs value, the caller of arch_prctl(ARCH_GET_GS, ...) will get back
      the value of some previous tasks's gs base value instead of 0.
      
          Change the arch_prctl() ARCH_GET_GS code to only read and return
          the MSR_KERNEL_GS_BASE msr register if the 'gs' register of the calling
          task is non-zero.
      
          Side note: Since in addition to using arch_prctl(ARCH_SET_GS, ...),
          a task can also setup a gs base value by using modify_ldt() and write
          an index value into 'gs' from user space, the patch below reads
          'gs' instead of using thread.gs, since in the modify_ldt() case,
          the thread.gs value will be 0, and incorrect value would be returned
          (the task->thread.gs value).
      
          When the user has not set its own gs base value and the 'gs'
          register is zero, then the MSR_KERNEL_GS_BASE register will not be
          read and a value of zero will be returned by reading and returning
          'task->thread.gs'.
      
          The first patch shown below is an attempt at implementing this
          approach.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      97c2803c
    • J
      [PATCH] x86_64: Fix drift with HPET timer enabled · b20367a6
      Jordan Hargrave 提交于
      If the HPET timer is enabled, the clock can drift by ~3 seconds a day.
      This is due to the HPET timer not being initialized with the correct
      setting (still using PIT count).
      
      If HZ changes, this drift can become even more pronounced.
      
      HPET patch initializes tick_nsec with correct tick_nsec settings for
      HPET timer.
      
      Vojtech comments:
      
        "It's not entirely correct (it assumes the HPET ticks totally
         exactly), but it's significantly better than assuming the PIT error
         there."
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      b20367a6
    • R
      [PATCH] x86_64: Fixup read_mostly section on internode cache line size for vSMP · e405d067
      Ravikiran G Thirumalai 提交于
      Fixup the read mostly section to start at internode cacheline boundary.
      Signed-off-by: NRavikiran Thirumalai <kiran@scalex86.org>
      Signed-off-by: NShai Fultheim <shai@scalex86.org>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e405d067
    • A
      3d34ee68