1. 20 8月, 2009 8 次提交
    • B
      powerpc: Use names rather than numbers for SPRGs (v2) · ee43eb78
      Benjamin Herrenschmidt 提交于
      The kernel uses SPRG registers for various purposes, typically in
      low level assembly code as scratch registers or to hold per-cpu
      global infos such as the PACA or the current thread_info pointer.
      
      We want to be able to easily shuffle the usage of those registers
      as some implementations have specific constraints realted to some
      of them, for example, some have userspace readable aliases, etc..
      and the current choice isn't always the best.
      
      This patch should not change any code generation, and replaces the
      usage of SPRN_SPRGn everywhere in the kernel with a named replacement
      and adds documentation next to the definition of the names as to
      what those are used for on each processor family.
      
      The only parts that still use the original numbers are bits of KVM
      or suspend/resume code that just blindly needs to save/restore all
      the SPRGs.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ee43eb78
    • B
      powerpc: Rename exception.h to exception-64s.h · 8aa34ab8
      Benjamin Herrenschmidt 提交于
      The file include/asm/exception.h contains definitions
      that are specific to exception handling on 64-bit server
      type processors.
      
      This renames the file to exception-64s.h to reflect that
      fact and avoid confusion.
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      8aa34ab8
    • A
      powerpc: Preload application text segment instead of TASK_UNMAPPED_BASE · de4376c2
      Anton Blanchard 提交于
      TASK_UNMAPPED_BASE is not used with the new top down mmap layout. We can
      reuse this preload slot by loading in the segment at 0x10000000, where almost
      all PowerPC binaries are linked at.
      
      On a microbenchmark that bounces a token between two 64bit processes over pipes
      and calls gettimeofday each iteration (to access the VDSO), both the 32bit and
      64bit context switch rate improves (tested on a 4GHz POWER6):
      
      32bit: 273k/sec -> 283k/sec
      64bit: 277k/sec -> 284k/sec
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      de4376c2
    • A
      powerpc: Rearrange SLB preload code · 5eb9bac0
      Anton Blanchard 提交于
      With the new top down layout it is likely that the pc and stack will be in the
      same segment, because the pc is most likely in a library allocated via a top
      down mmap. Right now we bail out early if these segments match.
      
      Rearrange the SLB preload code to sanity check all SLB preload addresses
      are not in the kernel, then check all addresses for conflicts.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      5eb9bac0
    • A
      powerpc: Move 64bit VDSO to improve context switch performance · 30d0b368
      Anton Blanchard 提交于
      On 64bit applications the VDSO is the only thing in segment 0. Since the VDSO
      is position independent we can remove the hint and let get_unmapped_area pick
      an area. This will mean the vdso will be near other mmaps and will share
      an SLB entry:
      
      10000000-10001000 r-xp 00000000 08:06 5778459        /root/context_switch_64
      10010000-10011000 r--p 00000000 08:06 5778459        /root/context_switch_64
      10011000-10012000 rw-p 00001000 08:06 5778459        /root/context_switch_64
      fffa92ae000-fffa92b0000 rw-p 00000000 00:00 0
      fffa92b0000-fffa9453000 r-xp 00000000 08:06 4334051  /lib64/power6/libc-2.9.so
      fffa9453000-fffa9462000 ---p 001a3000 08:06 4334051  /lib64/power6/libc-2.9.so
      fffa9462000-fffa9466000 r--p 001a2000 08:06 4334051  /lib64/power6/libc-2.9.so
      fffa9466000-fffa947c000 rw-p 001a6000 08:06 4334051  /lib64/power6/libc-2.9.so
      fffa947c000-fffa9480000 rw-p 00000000 00:00 0
      fffa9480000-fffa94a8000 r-xp 00000000 08:06 4333852  /lib64/ld-2.9.so
      fffa94b3000-fffa94b4000 rw-p 00000000 00:00 0
      
      fffa94b4000-fffa94b7000 r-xp 00000000 00:00 0        [vdso] <----- here I am
      
      fffa94b7000-fffa94b8000 r--p 00027000 08:06 4333852  /lib64/ld-2.9.so
      fffa94b8000-fffa94bb000 rw-p 00028000 08:06 4333852  /lib64/ld-2.9.so
      fffa94bb000-fffa94bc000 rw-p 00000000 00:00 0
      fffe4c10000-fffe4c25000 rw-p 00000000 00:00 0        [stack]
      
      On a microbenchmark that bounces a token between two 64bit processes over pipes
      and calls gettimeofday each iteration (to access the VDSO), our context switch
      rate goes from 268k to 277k ctx switches/sec (tested on a 4GHz POWER6).
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      30d0b368
    • G
      powerpc: expose the multi-bit ops that underlie single-bit ops. · 0d2d3e38
      Geoff Thorpe 提交于
      The bitops.h functions that operate on a single bit in a bitfield are
      implemented by operating on the corresponding word location. In all
      cases the inner logic is valid if the mask being applied has more than
      one bit set, so this patch exposes those inner operations. Indeed,
      set_bits() was already available, but it duplicated code from
      set_bit() (rather than making the latter a wrapper) - it was also
      missing the PPC405_ERR77() workaround and the "volatile" address
      qualifier present in other APIs. This corrects that, and exposes the
      other multi-bit equivalents.
      
      One advantage of these multi-bit forms is that they allow word-sized
      variables to essentially be their own spinlocks, eg. very useful for
      state machines where an atomic "flags" variable can obviate the need
      for any additional locking.
      Signed-off-by: NGeoff Thorpe <geoff@geoffthorpe.net>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      0d2d3e38
    • M
      powerpc/mpic: Fix MPIC_BROKEN_REGREAD on non broken MPICs · 11a6b292
      Michael Ellerman 提交于
      The workaround enabled by CONFIG_MPIC_BROKEN_REGREAD does not work
      on non-broken MPICs. The symptom is no interrupts being received.
      
      The fix is twofold. Firstly the code was broken for multiple isus,
      we need to index into the shadow array with the src_no, not the idx.
      Secondly, we always do the read, but only use the VECPRI_MASK and
      VECPRI_ACTIVITY bits from the hardware, the rest of "val" comes
      from the shadow.
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      11a6b292
    • G
      powerpc/amigaone: Convert amigaone_init() to a machine_device_initcall() · 66dc3304
      Gerhard Pircher 提交于
      This allows to remove the ppc_md.init() hook in the setup code.
      Signed-off-by: NGerhard Pircher <gerhard_pircher@gmx.net>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      66dc3304
  2. 19 8月, 2009 18 次提交
  3. 18 8月, 2009 12 次提交
  4. 17 8月, 2009 2 次提交
    • I
      x86, mce: Don't initialize MCEs on unknown CPUs · e412cd25
      Ingo Molnar 提交于
      An older test-box started hanging at the following point during
      bootup:
      
       [    0.022996] Mount-cache hash table entries: 512
       [    0.024996] Initializing cgroup subsys debug
       [    0.025996] Initializing cgroup subsys cpuacct
       [    0.026995] Initializing cgroup subsys devices
       [    0.027995] Initializing cgroup subsys freezer
       [    0.028995] mce: CPU supports 5 MCE banks
      
      I've bisected it down to commit 4efc0670 ("x86, mce: use 64bit
      machine check code on 32bit"), which utilizes the MCE code on
      32-bit systems too.
      
      The problem is caused by this detail in my config:
      
        # CONFIG_CPU_SUP_INTEL is not set
      
      This disables the quirks in mce_cpu_quirks() but still enables
      MCE support - which then hangs due to the missing quirk
      workaround needed on this CPU:
      
      	if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
      		mce_banks[0].init = 0;
      
      The safe solution is to not initialize MCEs if we dont know on
      what CPU we are running (or if that CPU's support code got
      disabled in the config).
      
      Also be a bit more defensive on 32-bit systems: dont do a
      boot-time dump of pending MCEs not just on the specific system
      that we found a problem with (Pentium-M), but earlier ones as
      well.
      
      Now this problem is probably not common and disabling CPU
      support is rare - but still being more defensive in something
      we turned on for a wide range of CPUs is prudent.
      
      Cc: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
      LKML-Reference: Message-ID: <4A88E3E4.40506@jp.fujitsu.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      e412cd25
    • B
      x86, mce: don't log boot MCEs on Pentium M (model == 13) CPUs · c7f6fa44
      Bartlomiej Zolnierkiewicz 提交于
      On my legacy Pentium M laptop (Acer Extensa 2900) I get bogus MCE on a cold
      boot with CONFIG_X86_NEW_MCE enabled, i.e. (after decoding it with mcelog):
      
      MCE 0
      HARDWARE ERROR. This is *NOT* a software problem!
      Please contact your hardware vendor
      CPU 0 BANK 1 MCG status:
      MCi status:
      Error overflow
      Uncorrected error
      Error enabled
      Processor context corrupt
      MCA: Data CACHE Level-1 UNKNOWN Error
      STATUS f200000000000195 MCGSTATUS 0
      
      [ The other STATUS values observed: f2000000000001b5 (... UNKNOWN error)
        and f200000000000115 (... READ Error).
      
        To verify that this is not a CONFIG_X86_NEW_MCE bug I also modified
        the CONFIG_X86_OLD_MCE code (which doesn't log any MCEs) to dump
        content of STATUS MSR before it is cleared during initialization. ]
      
      Since the bogus MCE results in a kernel taint (which in turn disables
      lockdep support) don't log boot MCEs on Pentium M (model == 13) CPUs
      by default ("mce=bootlog" boot parameter can be be used to get the old
      behavior).
      Signed-off-by: NBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
      Reviewed-by: NAndi Kleen <andi@firstfloor.org>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      c7f6fa44