With commit c716483c ("ARM: 8122/1: smp_scu: enable SCU standby
support"), the STANDBY bit of SCU is handled by core function
scu_enable().  So imx_scu_standby_enable() can be removed now.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

pcm970-baseboard.c and mach-pcm038.c can be replaced with their
devicetree equivalents: imx27-phytec-phycore-rdk.dts and
imx27-phytec-phycore-som.dtsi respectively, so remove the board files.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

eukrea_mbimx27-baseboard.c and mach-cpuimx27.c can be replaced with their
devicetree equivalents: imx27-eukrea-mbimxsd27-baseboard.dts and
imx27-eukrea-cpuimx27.dtsi respectively, so remove the board files.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NEric Bénard <eric@eukrea.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The iomux function declarations are in headers only accessible in this
directory. Thus those can't be used in any module. None of the
objects in this directory is tristate. Neither can the header be included
in out-of-tree modules.
Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

On i.MX6Q, gpu2d_axi and gpu3d_axi are either from AXI or
AHB clock, but on i.MX6DL, gpu2d_axi and gpu3d_axi are
from mmdc_ch0_axi_podf, and they can NOT be gated by mmdc_ch0_axi
's clock gate, the mux option register field(CCM_CBCMR)
is marked as "Reserved" now on i.MX6DL RM, so correct these
two clks setting.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Since ARCH_MXC already selects ARCH_HAS_OPP, it's really unnecessary for
SOC_IMX27 and SOC_IMX5 to select it again.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

After the suspend routine running in OCRAM puts DDR into self-refresh,
it will access IOMUXC block to float DDR IO for power saving.  A TLB
missing of IOMUXC base address may happen in this case, and triggers an
access to DDR, and thus hangs the system.

The failure is discovered by running suspend/resume on a Cubox-i board.
Though the issue is not Cubox-i specific, it can be hit the on the board
quite easily with the 3.15 or 3.16 kernel.

Fix the issue with a dummy access to IOMUXC block at the beginning of
suspend routine, so that the address translation can be filled into TLB
before DDR is put into self-refresh.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
Cc: <stable@vger.kernel.org>
Acked-by: NAnson Huang <Anson.Huang@freescale.com>

My earlier patch 1fc593fe ("ARM: imx: build i.MX6 functions
only when needed") fixed a problem with building an i.MX5 kernel,
but now the problem has returned for the case where we allow
ARMv6K SMP builds in multiplatform. With CONFIG_CPU_V7 disabled,
but i.MX3 and SMP enabled, we get this build error:

arch/arm/mach-imx/built-in.o: In function `v7_secondary_startup':
:(.text+0x5124): undefined reference to `v7_invalidate_l1'

This puts the code inside of an "ifdef CONFIG_SOC_IMX6" to hopefully
do the right thing in all configurations.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The bus devices created to be parents for other peripherals
were using platform_bus as a parent, not being platform
devices themselves. Remove the references, making them
virtual devices instead.

Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Acked-by: NShawn Guo <shawn.guo@freescale.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

A number of board files in arch/arm and arch/unicore32
explicitly reference platform_bus device as a parent
for new platform devices.

This is unnecessary, as platform device API guarantees
that devices with NULL parent are going to by adopted
by the mentioned "root" device.

This patch removes or replaces with NULL such references.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Acked-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

Since the OPP layer is a kernel library which has been converted to be
directly selectable by its callers rather than user selectable and
requiring architectures to enable it explicitly the ARCH_HAS_OPP symbol
has become redundant and can be removed. Do so.
Signed-off-by: NMark Brown <broonie@linaro.org>
Reviewed-by: NViresh Kumar <viresh.kumar@linaro.org>
Acked-by: NNishanth Menon <nm@ti.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NShawn Guo <shawn.guo@freescale.com>
Acked-by: NSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>

ARMv6 and greater introduced a new instruction ("bx") which can be used
to return from function calls.  Recent CPUs perform better when the
"bx lr" instruction is used rather than the "mov pc, lr" instruction,
and this sequence is strongly recommended to be used by the ARM
architecture manual (section A.4.1.1).

We provide a new macro "ret" with all its variants for the condition
code which will resolve to the appropriate instruction.

Rather than doing this piecemeal, and miss some instances, change all
the "mov pc" instances to use the new macro, with the exception of
the "movs" instruction and the kprobes code.  This allows us to detect
the "mov pc, lr" case and fix it up - and also gives us the possibility
of deploying this for other registers depending on the CPU selection.
Reported-by: NWill Deacon <will.deacon@arm.com>
Tested-by: Stephen Warren <swarren@nvidia.com> # Tegra Jetson TK1
Tested-by: Robert Jarzmik <robert.jarzmik@free.fr> # mioa701_bootresume.S
Tested-by: Andrew Lunn <andrew@lunn.ch> # Kirkwood
Tested-by: NShawn Guo <shawn.guo@freescale.com>
Tested-by: Tony Lindgren <tony@atomide.com> # OMAPs
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> # Armada XP, 375, 385
Acked-by: Sekhar Nori <nsekhar@ti.com> # DaVinci
Acked-by: Christoffer Dall <christoffer.dall@linaro.org> # kvm/hyp
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> # PXA3xx
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> # Xen
Tested-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> # ARMv7M
Tested-by: Simon Horman <horms+renesas@verge.net.au> # Shmobile
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Extend the clock control for FlexCAN with the second gate which
enable the clocks in the Clock Divider (CCM_CSCDR2) register too.
Signed-off-by: NStefan Agner <stefan@agner.ch>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch uses clocksource_of_init() call for DT targets.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Most peripherals on the i.MX53 have an
  Off-Platform Peripheral Access Control Register (OPACR)
in which the access rights (together with the MPROT registers) can be declared.
However, this does not seem to work for example for SSI1+SDMA, because the
supervisor bit is not set for the SDMA unit.
It does work for SSI2, the QSB for example uses SSI2 for its audio. But SSI2 only
works because it does NOT have an OPACR.

The right solution would be to fix the access rights for the SDMA, but the unit
responsible for this is the Central Security Unit (CSU), which of course is NOT
documented. So, until documentation for this is openly available, turn off the
supervisor protection because it cripples the hardware.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The i.MX SoCs allow to setup fine grained access rights to peripherals on the
AIPS bus.
This is done via the Peripheral Access Register (PAR) in e.g. the i.MX21
or in later SoC versions the Off-Platform Peripheral Access Control Register
(OPACR), e.g. i.MX53.
Under certain circumstances this leads to problems in which bus masters are
not granted their access rights to peripherals.
To be able to disable these restrictions on DT platforms, add a helper function
that looks for AIPS nodes in the DT and disables them for every compatible node
it finds.
The compatible has to be declared in the mach-specific entry file, where this
helper function should then be called.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch adds missing 26 MHz oscillator circuit clock gate support.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch removes definitions which not used anywhere in the driver.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Use clock defines in order to make devicetrees more human readable.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The board has no insufficient support to be fully functional and seems
has no users. This patch removes support for this board.
However, the support may be added in the future by using the devicetree.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch removes excess symbols ARCH_MX1, ARCH_MX25 and MACH_MX27.
Instead we use SOC_IMX*.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

i.MX1 camera driver has been removed by the commit 90b05589.
This patch removes remaining support files for this camera.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

replace IS_ERR/PTR_ERR

Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NFabian Frederick <fabf@skynet.be>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

imx6q_pm_enter calls imx6sl_set_wait_clk when run on an imx6sl
based machine. However if support for imx6sl is not enabled
at compile time, this prevents us from building the kernel and
we get this link error instead:

arch/arm/mach-imx/built-in.o: In function `imx6q_pm_enter':
:(.text+0x4b84): undefined reference to `imx6sl_set_wait_clk'

This makes the cpu_is_imx6sl function conditionally return false
if imx6sl is disabled at compile-time, which matches what the
older cpu_is_mx* macros did. We have similar inline functions for
the other imx6 variants, but so far I have not run into a case
where the extra #ifdef is necessary.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Building a kernel for imx6sx but without imx6q support results in
this link error because of the missing cpuidle driver:

arch/arm/mach-imx/built-in.o: In function `imx6sx_init_late'::(.init.text+0xc228):
 undefined reference to `imx6q_cpuidle_init'

This patch adds a Makefile entry so we always build support for
the imx6q_cpuidle code when at least one of the 6sx or 6q variants
are enabled.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The PL310 integrated on i.MX6 series and VF610 are revision r3p1 and
later.  Per ARM PL310 errata document, 588369 is fixed in r2p0 and
727915 is fixed in r3p1.  Neither is needed for i.MX6 or VF610.  So
let's drop them.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

SSI and SSI_IPG are clocks controlled by the same clock gating field, so
register them with imx_clk_gate2_shared.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Otherwise GCC will mark the .init.rodata section R/W, which causes
a compile error once we add other real R/O data.
Signed-off-by: NLucas Stach <l.stach@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

It is only the mx6quad variant that can run up to 1.2GHz, so add the check
accordingly.

This avoids getting the following warning on a mx6solo:

failed to disable 1.2 GHz OPP
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Replace .init_time() hook with of_clk_init() for DT targets.

Based on:
  d4347ee ARM: i.MX27 clk: Use of_clk_init() for DT case
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

The gpt0 timer clock has been wrong since:
  6bbaec56 ARM i.MX25: implement clocks using common clock framework
Signed-off-by: NDenis Carikli <denis@eukrea.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch adds devicetree support CCM module for i.MX21 CPUs.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This is a cleanup for i.MX21 clk driver. This change includes:
- Reduce license text.
- Remove unused definitions.
- Remove unused #include and sort the rest.
- Remove useless comment.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch removes clk_register_clkdev() for the clocks that do not
have any users for boards and drivers.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

This patch perform rework i.MX21 clock initialization. This includes
adding missing clocks and sort clocks by register address.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

mx51 and mx53 are device tree only platforms, so we no longer need all these
calls to clk_register_clkdev().

Only keep cpu0 and gpc_dvfs clk_register_clkdev() calls.

Tested on imx51-babbage and imx53-qsb boards.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add standby mode support for suspend, to enter standby mode:

echo standby > /sys/power/state;

Use UART or RTC alarm to wake up system, when system enters
standby mode, SOC will enter STOP mode with ARM core kept
power on and 24M XTAL on.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Instead of using enum for clock ID, let's switch imx6qdl clock driver to
use macro.  In this case, device tree can reuse these macros to improve
readability.
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>

Add cpuidle support for i.MX6SX, derive from i.MX6Q's
cpuidle, two levels supported:

1. WFI;
2. WAIT mode.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@freescale.com>