Use devicetree to define NAND partitions. Use D-link partition scheme by
default, to be vaguely compatible with their userland.

Changes since last submission (V4):-
* Don't add NAND support then throw it away immediately after [Grant Likely]
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NJamie Lentin <jm@lentin.co.uk>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add default configuration for NAND, to be enabled in your board config. Ensure
clock gating is set appropriately when the NAND is enabled.
Acked-by: NJason Cooper <jason@lakedaemon.net>
Signed-off-by: NJamie Lentin <jm@lentin.co.uk>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add support for the DNS-320 and DNS-325. Describe as much as currently possible
in the devicetree files, create a board-dnskw.c for everything else.

Changes since last submission (V3) [Addressing comments by]:-

* One MACH_DLINK_KIRKWOOD_DT for all dtb files [Grant Likely, Jason Cooper]
* Drop brain-dead select "select CONFIG_MTD_OF_PARTS" [Grant Likely]
* Don't add NAND support then throw it away immediately after [Grant Likely]
* Describe purpose of MPP 41, 42 & 49

Changes since last submission (V2):-

* Use IEEE-compliant "okay", rather than "ok" [Scott Wood]
Signed-off-by: NJamie Lentin <jm@lentin.co.uk>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

As of

    commit 75294957
    Author: Grant Likely <grant.likely@secretlab.ca>
    Date:   Tue Feb 14 14:06:57 2012 -0700

        irq_domain: Remove 'new' irq_domain in favour of the ppc one

the ARM gic controller uses proper irq domains.  Fix the MSM gic
initialization and DT so that it works again.
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>

The MMCI driver will not work without two IRQs since this is not
flagged as a single-irq variant. Looking through the complex IRQ
definition for the MMCI on the versatile (including an #if 1
statement forcing MMCI IRQ0 to the VIC) this appears to the the
correct IRQ number for both models.

Cc: Niklas Hernaeus <niklas.hernaeus@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

These were incorrectly introduced and can cause problems for of_irq_init.

The correct way to define a root controller is no interrupt-parent set at
all or the interrupt-parent is set to the root controller itself when
inherited from a parent node.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>
Tested-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Because of the inclusion of skeleton.dtsi, the memory node is
named "memory" we where not modifying the already included one
but creating a new one. It caused bad memory node detection during
early_init_dt_scan_memory() so we modify them.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Change vbus gpio configuration in .dts files to switch to
active low configuration.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: stable <stable@vger.kernel.org>

This patch adds a generic target for SPEAr600 board that can be
configured via the device-tree. Currently the following devices
are supported via the devicetree:

- VIC interrupts
- PL011 UART
- PL061 GPIO
- Synopsys DW I2C
- Synopsys DW ethernet

Other peripheral devices (e.g. SMI flash, FSMC NAND flash etc) will
follow in later patches.

Only the spear600-evb is currently supported. Other SPEAr600
based boards will follow later.

Since the current mainline SPEAr600 code only supports the SPEAr600
evaluation board, with nearly zero peripheral devices (only UART
and GPIO), it makes sense to switch over to DT based configuration
completely now. So this patch also removes all non-DT stuff, mainly
platform device data. The files spear600.c and spear600_evb.c are
removed completely.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This enables local timer (AKA: private timer) support for
all u8500 based hardware using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This SSP Controller supports a number of serial communication methods
and as such cannot be registered using of_register_spi_devices.
Instead we register it simply as a primecell device.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This provides PL310 Level 2 Cache Controller Device Tree
support for all u8500 based devices.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Enables the 3 UARTs found on a u8500 using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This enables the embedded GIC on all u8500 based hardware using DT.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This adds all devices that are normally present through the
u8500_init_machine function in the device tree as well, which
will duplicate the devices that are visible.

This will not do much by itself because the device from the
device tree are not matched by any device driver until they
are converted as well. The next step is to move over one
device at a time to actually be used from the device tree
instead of the hardcoded device using auxdata to pass the
correct platform_data.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

db8500.dtsi can be used by all systems with a db8500 or
db9500 SoC, while snowball.dts is board specific.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This provides very basic Device Tree support for ST-Ericsson's
low-cost development platform, Snowball. If Device Tree for
ux500 is enabled and the correct board is configured within the
Device Tree blob, the correct *_init_machine() will be called.

This patch is based on some original work completed by:
  Niklas Hernaeus <niklas.hernaeus@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NNiklas Hernaeus <niklas.hernaeus@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NJason Cooper <jason@lakedaemon.net>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Define both uarts in kirkwood.dtsi as they are common to all kirkwood
SoCs.  Each board may enable all or none of them, so they are disabled
by default.  uart0 is enabled for the dreamplug.

tclk can vary for each board, so we leave it undefined in the kirkwood
dtsi.  Each board can then set it as appropriate when enabling the uart.
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Also, use inclusive register size for uart0.
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

make the ECHI depends on ARCH_AT91
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: devicetree-discuss@lists.ozlabs.org

Use a string to specific the wakeup mode to make it more readable.

Add the Real-time Clock Wake-up support too for sam9g45 and sam9x5.
Add AT91_SHDW_CPTWK0_MAX to specific the Max of the Wakeup Counter.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

We can now drop the call to ioremap_registers() as we have the binding for the
SDRAM/DDR Controller.

Drop ioremap_registers() for sam9x5 too.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Specified the main Oscillator via clock binding.
This will allow to do not hardcode it anymore in the DT board at 12MHz.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NNicolas Ferre <nicolas.ferre@atmel.com>

http://www.calao-systems.com/articles.php?lng=en&pg=6099

this daughter board add the following device:
 - Micro-SD socket
 - TTL 3V3 - (Tx/Rx/RTS/CTS)
 - I2C port
 - 0.96" Serial OLED Display Module (over UART)
 - MP3 decoder with Micro & Speakers
 - 4x PB, 4x Leds (Blue), 3x Leds (Green, Orange, Red)

for now we add only the 2 UARTs, 4 Buttons, 7 leds and i2c via DT

used_led1 will not be re-add via DT as it's used by the motherboard too
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

Use i2c-gpio and enable rv3029 RTC.

Enable the rtc in the sam9g20 defconfig.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

For now on use i2c-gpio driver on the same pin as the hardware IP.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

Enable the nand in the cpu module with the partition.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Use a local copy of board informatin and fill with DT data.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Nicolas Ferre <nicolas.ferre@atmel.com>

This patch adds initial dts file for EXYNOS5250 SoC. This dts
file is including the SoC specific devices and properties. And
adds the dts file for SMDK5250 board which uses the EXYNOS5250
dts file. Its board specific properites will be added later.

Cc: Thomas Abraham <thomas.abraham@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Add support for the new smp_twd runtime registration interface
to the imx6q platforms, and remove the old compile-time support.

The imx6q DTS file is updated to match the TWD DT documentation.
Also present in this patch a DTS fix to the timer interrupt routing
(the PPI connection uses bits [15:8]) and trigger (rising edge).
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add support for the new smp_twd runtime registration interface
to the highbank platforms, and remove the old compile-time support.

The highbank DTS file is updated to match the TWD DT documentation
and fixes the timer trigger (rising edge).
Acked-by: NRob Herring <rob.herring@calxeda.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The USB1 port on Tegra2 supports operation in host or device modes. On
Seaboard this is possible, so mark the port as OTG.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Tegra's USB1 port supports legacy mode, so mark it as such. Even if we
don't use it, we must turn it off in the driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>