- 19 6月, 2013 1 次提交
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由 Guennadi Liakhovetski 提交于
To disable spurious interrupts, that get triggered on certain hardware, the irqpin driver masks them on the parent interrupt controller. To specify such broken devices a .control_parent parameter can be provided in the platform data. In the DT case we need a property, to do the same. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 18 6月, 2013 1 次提交
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由 Guennadi Liakhovetski 提交于
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 28 3月, 2013 1 次提交
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由 Bastian Hecht 提交于
On some hardware we don't have a 1-1 mapping from the external interrupts coming from INTC to the GIC SPI pins. We can however share lines to demux incoming IRQs on these SoCs. This patch enables the intc_irqpin driver to detect requests for shared interrupt lines and demuxes them properly by querying the INTC INTREQx0A registers. If you need multiple shared intc_irqpin device instances, be sure to mask out all interrupts on the INTC that share the one line before you start to register them. Else you run into IRQ floods that would be caused by interrupts for which no handler has been set up yet when the first intc_irqpin device is registered. Signed-off-by: NBastian Hecht <hechtb+renesas@gmail.com> Acked-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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- 18 3月, 2013 6 次提交
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由 Magnus Damm 提交于
Add initial DT support to the INTC External IRQ Pin driver. At this point only hardware with 4-bit wide sense registers is supported via DT. Signed-off-by: NMagnus Damm <damm@opensource.se> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Use devm_kzalloc(), devm_ioremap_nocache() and devm_request_irq() to simplify error handling. Signed-off-by: NMagnus Damm <damm@opensource.se> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Tested-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Add comments to describe the special case for "force" versions of enable and disable functions. Signed-off-by: NMagnus Damm <damm@opensource.se> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Tested-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Cache IRQ in domain_irq variable instead of making use of irq_find_mapping(). While at it rename the irq variable to requested_irq. Signed-off-by: NMagnus Damm <damm@opensource.se> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Tested-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
Remove whitespace damage and add newline between variables and code. Signed-off-by: NMagnus Damm <damm@opensource.se> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Tested-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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由 Magnus Damm 提交于
This patch adds a driver for external IRQ pins connected to the INTC block on recent SoCs from Renesas. The INTC hardware block usually contains a rather wide range of features ranging from external IRQ pin handling to legacy interrupt controller support. On older SoCs the INTC is used as a general purpose interrupt controller both for external IRQ pins and on-chip devices. On more recent ARM based SoCs with Cortex-A9 the main interrupt controller is the GIC, but IRQ trigger setup still need to happen in the INTC hardware block. This driver implements the glue code needed to configure IRQ trigger and also handle mask/unmask and demux of external IRQ pins hooked up from the INTC to the GIC. Tested on sh73a0 and r8a7779. The hardware varies quite a bit with SoC model, for instance register width and bitfield widths vary wildly. The driver requires one GIC SPI per external IRQ pin to operate. Each driver instance will handle up to 8 external IRQ pins. The SoCs using this driver are currently mainly used together with regular platform devices so this driver allows configuration via platform data to support things like static interrupt base address. DT support will be added incrementally in the not so distant future. Signed-off-by: NMagnus Damm <damm@opensource.se> Acked-by: NThomas Gleixner <tglx@linutronix.de> Signed-off-by: NSimon Horman <horms+renesas@verge.net.au>
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