This alters the local side address of the iospace to zero,
non prefetchable memory local side address to 0x00000000 and
prefetchable memory local side address to 0x10000000,
so as to match the values actually poked in by the driver.
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds pcie controller node for exynos5440-ssdk5440,
and also adds a phandle for pin controller node.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Exynos5440 has two PCIe controllers which can be used as root complex
for PCIe interface.
Signed-off-by: NJingoo Han <jg1.han@samsung.com>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: NWenyou Yang <wenyou.yang@atmel.com>

In previous version of SPI driver we where using different compatibility stings
for finding SPI features. We are now using the IP revision information.
So we stay with the unique compatibility string for this driver:
"atmel,at91rm9200-spi".
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Tested-by: NWenyou Yang <wenyou.yang@atmel.com>

The length of the registers area for the Marvell 370/XP Ethernet controller
was incorrect in the .dtsi: 0x2500, while it should have been 0x4000.
This problem wasn't noticed because there used to be a static mapping for
all the MMIO register region set up by ->map_io().

The register length was fixed in all the other device tree files,
except from the armada-xp-mv78260.dtsi, in the following commit:

  commit cf8088c5
  Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  Date:   Tue May 21 12:33:27 2013 +0200

    arm: mvebu: fix length of Ethernet registers area in .dtsi

This commit fixes a kernel panic in mvneta_probe(), when the kernel
tries to access the unmapped registers:

[  163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e
[  163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef
[  163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c
[  163.661258] Unable to handle kernel paging request at virtual address f011bcf0
[  163.668523] pgd = c0004000
[  163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000
[  163.677565] Internal error: Oops: 807 [#1] SMP ARM
[  163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11
[  163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000
[  163.695467] PC is at mvneta_probe+0x34c/0xabc
[...]
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Although the internal register window size is 1 MiB, the previous
ranges translation for the internal register space had a size of
0x4000000. This was done to allow the crypto and nand node to access
the corresponding 'sram' and 'nand' decoding windows.

In order to describe the hardware more accurately, we declare the
real 1 MiB internal register space in the ranges, and add a translation
entry for the nand node to access the 'nand' window.

This commit will make future improvements on the MBus DT binding easier.
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This adds a generic devicetree board file and a dtsi for boards
based on the RK3066a SoCs from Rockchip.

Apart from the generic parts (gic, clocks, pinctrl) the only components
currently supported are the timers, uarts and mmc ports (all DesignWare-
based).
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NOlof Johansson <olof@lixom.net>

This adds a basic clock setup for rk3066a SoCs. Only the gates are
set up currently, as the mux and dividers should use the upcoming
generic devicetree bindings.

Clocks whose rates need to be known are supplied by fixed-rate
"dummy"-clocks that provide the correct rate. This is uncritical insofar
that the only bootloader currently in existence for Rockchip devices
is the propietary Rockchip one that always setups the clocks in the
necessary way.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Reviewed-by: NMike Turquette <mturquette@linaro.org>

CodingStyle does not allow C99 style comments. Since the
dts files live in the kernel for now, make this compliant.
Signed-off-by: NMatt Porter <matt.porter@linaro.org>
Acked-by: NChristian Daudt <csd@broadcom.com>

Add SDHCI bindings for the Broadcom 281xx SoCs.

Changes from V2:
 - Documentation cleanups

Changes from V1:
 - split original patch into 2, one for driver and this one for dt
Signed-off-by: NChristian Daudt <csd@broadcom.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

This revamps the device tree to fit with the new clock
implementation and brings it quite a bit closer to how
the hardware actually works.

After this the clock implementation knows about all
clock gates and will gate off all unused clocks at
boot time and save a bit of power.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

USB Host PHY clock on port 2 must be configured to 19.2MHz.
Provide this information.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

On Panda the +5V supply for DVI EDID is supplied by the
same regulator that poweres the USB Hub. Currently, the
DSS/DVI subsystem doesn't know how to manage this regulator
and so DVI EDID reads will fail if USB Hub is not enabled.

As a temporary fix we keep this regulator permanently enabled
on boot. This fixes the DVI EDID read problem.

CC: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Provide the RESET and Power regulators for the USB PHY,
the USB Host port mode and the PHY device.

Also provide pin multiplexer information for the USB host
pins.

HACK: The reset control need to be replaced with the proper
gpio-controlled reset driver as soon it will be merged [1].
[1] http://thread.gmane.org/gmane.linux.drivers.devicetree/36830Signed-off-by: NRoger Quadros <rogerq@ti.com>
[benoit.cousson@linaro.org: Add disclaimer about the reset control
inside changelog and code]
Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The Armada 370 RD board has two internal mini-PCIe connectors. This
commit adds the necessary Device Tree informations to enable the usage
of those mini-PCIe connectors.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Florian Fainelli <florian@openwrt.org>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Add AM43x ePOS EVM minimal DT source - this is a minimal one to get
it booting. Also include it in omap2plus dtbs and document bindings.
The hardware is under development.
Signed-off-by: NAfzal Mohammed <afzal@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add bandgap device DT entry for OMAP5 dtsi.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
[benoit.cousson@linaro.org: Fix alignement and use the macros
for IRQ attributes]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add pinmux configurations for RGMII based CPSW ethernet to am335x-evm.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add pinmux configurations for RGMII based CPSW ethernet to AM335x EVMsk.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add pinmux configurations for MII based CPSW ethernet to am335x-bone.

Default mode is nothing but the values required for the module during
active state. With this configurations module is functional as
expected.

Sleep mode is nothing but the values required for the module during
inactive state. The pins are configured to its reset state to optimize
energy usage for the pins for the suspend/resume cycle
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Commit c971ff18 'leds: leds-pwm: Defer led_pwm_set() if PWM can sleep'
fixed a crash when using a trigger with a pwm-led provided by an
external chip. Now it is safe to add the default trigger according
to board-overo.c.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The LED is active low, not active high.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

The Tobi expansion boards embeds a SMSC LAN8700 PHY. Add the
corresponding node into the DT. The regulators are not designed
to be turned off.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Some nodes in OMAP3 DTS now use edge or level sensitive interrupts.
Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Acked-by: NEmilio López <emilio@elopez.com.ar>

Add Palmas MFD node and the regulator nodes for OMAP5.

The node definitions are based on: https://lkml.org/lkml/2013/6/6/25

Boot tested on omap5-uevm board.
Signed-off-by: NGraeme Gregory <gg@slimlogic.co.uk>
Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

PWM output from ecap2 uses as backlight source. Also adds low threshold
value to have a uniform divisions in brightness-levels scales with
inverse polarity.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

PWM output from ecap0 uses as backlight source. Also adds low threshold
value to have a uniform divisions in brightness-levels scales.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add PWMSS device tree nodes in relation with ECAP & EHRPWM DT nodes to
AM33XX SoC family. Also populates device tree nodes for ECAP & EHRPWM by
adding necessary properties like pwm-cells, base reg & set disabled as
status.
Signed-off-by: NPhilip Avinash <avinashphilip@ti.com>
Reviewed-by: NThierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add bandgap devices for OMAP4460 devices.
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add the bandgap entry for OMAP4430 devices.
Signed-off-by: NEduardo Valentin <eduardo.valentin@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
[benoit.cousson@linaro.org: Add blank line and fix reg presentation]
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

On most OMAP3 platforms, the twl4030 IRQ line is connected to the
SYS_NIRQ line on OMAP.  Add another DTS include file
(twl4030_omap3.dtsi) for boards that hook up the twl4030 this way
to include.

This allows RTC wake from off-mode to work again on OMAP3-based
platforms with twl4030.  Tested on 3530/Beagle, 3730/Beagle-xM,
3530/Overo, 3730/Overo-STORM.

Special thanks to Florian Vaussard for suggesting use of preprocessor
feature.

Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Using the gpio-keys bindings, configure the user button on Beagle
boards.  Since the user button is enabled as a wakeup source, also
ensure the GPIO pin is mux'd correctly and has IO ring wakeups enabled,
so it can also wakeup from off mode.

Special thanks to Florian Vaussard for suggesting the preprocessor
feature.

Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Ensure the console uart (UART3) on these boards is mux'd correctly, and
IO ring wakeup is enabled.

This is needed for serial console wakeups when using DT boot.

Thanks to Florian Vaussard for suggestion to use preprocessor
features.

Cc: Florian Vaussard <florian.vaussard@epfl.ch>
Signed-off-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Booting omap5 uevm results in the following error
"did not get pins for uart error: -19"

This happens because omap5 uevm dts file is not adapted
to use uart through pinctrl framework.
Populate uart pinctrl data to get rid of the error.
Signed-off-by: NSourav Poddar <sourav.poddar@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>

Add support for blue LED 1 off of GPIO 153.
Make the LED a heartbeat LED
Configure the MUX for GPIO output.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
[r.sricharan@ti.com: Replaced constants with preprocessor macros]
Signed-off-by: NSricharan R <r.sricharan@ti.com>
Signed-off-by: NBenoit Cousson <benoit.cousson@linaro.org>