1. 20 6月, 2013 1 次提交
    • L
      clk: nomadik: implement the Nomadik clocks properly · ef6eb322
      Linus Walleij 提交于
      The Nomadik clock implementation was a stub just using
      fixed clocks.
      
      This implements the clocks properly instead of relying
      on them all being on at boot and leaving them all on.
      
      The PLLs are on the top locking to the main chrystal
      oscillator, then the HCLK for the peripherals are
      below PLL2.
      
      The gated clocks are implemented with zero cells and
      given the clock ID as a property of each node, so every
      gate need to have its own node in the device tree.
      This is because the gate registers contain both HCLK
      gates and PCLK gates, where the latter has HCLK as
      parent. As can be seen from the register layout, this
      is a complete mixup, which means all these gates need
      their own node to properly model parent/child relations
      for PCLKs apart from the HCLKs.
      
      This driver also adds a helpful debugfs file to inspect
      the hardware state of the clock gates.
      
      This is the end result in <debugfs>/clk/clk_summary
      after applying a proper device tree:
      
      ulpiclk                0   0    60000000
      mxtal                  3   3    19200000
         pll2                1   1    864000000
            clk48            3   3    48000000
               rngcclk       1   1    48000000
               usbmclk       0   0    48000000
               mshcclk       0   0    48000000
               mspclk3       0   0    48000000
               x3dclk        0   0    48000000
               skeclk        0   0    48000000
               owmclk        0   0    48000000
               mspclk2       0   0    48000000
               mspclk1       0   0    48000000
               uart2clk      0   0    48000000
               ipbmcclk      0   0    48000000
               ipi2cclk      0   0    48000000
               usbclk        0   0    48000000
               mspclk0       0   0    48000000
               uart1clk      1   2    48000000
               i2c1clk       0   0    48000000
               i2c0clk       0   0    48000000
               sdiclk        1   1    48000000
               uart0clk      0   0    48000000
               sspiclk       0   0    48000000
               irdaclk       0   0    48000000
            clk72            0   0    72000000
               difclk        0   0    72000000
               clcdclk       0   0    72000000
            clk216           0   0    216000000
               hsiclkrx      0   0    216000000
               clk108        0   0    108000000
                  hsiclktx   0   0    108000000
                  clk27      0   0    27000000
         pll1                1   1    264000000
            hclk             3   3    264000000
               hclkrng       1   1    264000000
               hclkusbm      0   0    264000000
               hclkcryp      0   0    264000000
               hclkhash      0   0    264000000
               hclk3d        0   0    264000000
               hclkhpi       0   0    264000000
               hclksva       0   0    264000000
               hclksaa       0   0    264000000
               hclkdif       0   0    264000000
               hclkusb       0   0    264000000
               hclkclcd      0   0    264000000
               hclkdma1      0   0    264000000
               hclksdram     0   0    264000000
               hclksmc       1   1    264000000
               hclkdma0      0   0    264000000
               pclk          7   9    264000000
                  pclkmsp3   0   0    264000000
                  pclkmshc   0   0    264000000
                  pclkhsem   0   0    264000000
                  pclkske    0   0    264000000
                  pclkowm    0   0    264000000
                  pclkmsp2   0   0    264000000
                  pclkmsp1   0   0    264000000
                  pclkuart2  0   0    264000000
                  pclkxti    0   0    264000000
                  pclkhsi    0   0    264000000
                  pclkmsp0   0   0    264000000
                  pclkuart1  1   1    264000000
                  pclki2c1   0   0    264000000
                  pclki2c0   0   0    264000000
                  pclksdi    1   1    264000000
                  pclkuart0  1   1    264000000
                  pclkssp    0   0    264000000
                  pclkirda   0   0    264000000
         timclk              1   1    2400000
      Acked-by: NMike Turquette <mturquette@linaro.org>
      Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      ef6eb322
  2. 17 6月, 2013 7 次提交
  3. 12 6月, 2013 2 次提交
  4. 29 5月, 2013 3 次提交
    • H
      ARM: tegra114: create a DT header defining CLK IDs · 992bb598
      Hiroshi Doyu 提交于
      Create a header file to define the clock IDs used by the Tegra114 clock
      binding. Remove the list of definitions from the binding documentation,
      and refer the reader to the header file.
      
      This will allow the same header to be used by both device tree files,
      and drivers implementing this binding, which guarantees that the two
      stay in sync. This also makes device trees more readable by using names
      instead of magic numbers.
      Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
      [swarren, add header to clock/ instead of clk/ to match binding location]
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      992bb598
    • H
      ARM: tegra30: create a DT header defining CLK IDs · 9513109d
      Hiroshi Doyu 提交于
      Create a header file to define the clock IDs used by the Tegra30 clock
      binding. Remove the list of definitions from the binding documentation,
      and refer the reader to the header file.
      
      This will allow the same header to be used by both device tree files,
      and drivers implementing this binding, which guarantees that the two
      stay in sync. This also makes device trees more readable by using names
      instead of magic numbers.
      Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
      [swarren, add header to clock/ instead of clk/ to match binding location]
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      9513109d
    • H
      ARM: tegra20: create a DT header defining CLK IDs · ec23ad67
      Hiroshi Doyu 提交于
      Create a header file to define the clock IDs used by the Tegra20 clock
      binding. Remove the list of definitions from the binding documentation,
      and refer the reader to the header file.
      
      This will allow the same header to be used by both device tree files,
      and drivers implementing this binding, which guarantees that the two
      stay in sync. This also makes device trees more readable by using names
      instead of magic numbers.
      Signed-off-by: NHiroshi Doyu <hdoyu@nvidia.com>
      [swarren, add header to clock/ instead of clk/ to match binding location]
      Signed-off-by: NStephen Warren <swarren@nvidia.com>
      ec23ad67
  5. 27 5月, 2013 2 次提交
  6. 15 4月, 2013 1 次提交
    • D
      ARM: socfpga: Add clock entries into device tree · 042000b0
      Dinh Nguyen 提交于
      Adds the main PLL clock groups for SOCFPGA into device tree file
      so that the clock framework to query the clock and clock rates
      appropriately.
      
      $cat /sys/kernel/debug/clk/clk_summary
         clock                        enable_cnt  prepare_cnt  rate
      ---------------------------------------------------------------------
       osc1                           2           2            25000000
          sdram_pll                   0           0            400000000
             s2f_usr2_clk             0           0            66666666
             ddr_dq_clk               0           0            200000000
             ddr_2x_dqs_clk           0           0            400000000
             ddr_dqs_clk              0           0            200000000
          periph_pll                  2           2            500000000
             s2f_usr1_clk             0           0            50000000
             per_base_clk             4           4            100000000
             per_nand_mmc_clk         0           0            25000000
             per_qsi_clk              0           0            250000000
             emac1_clk                1           1            125000000
             emac0_clk                0           0            125000000
          main_pll                    1           1            1600000000
             cfg_s2f_usr0_clk         0           0            100000000
             main_nand_sdmmc_clk      0           0            100000000
             main_qspi_clk            0           0            400000000
             dbg_base_clk             0           0            400000000
             mainclk                  0           0            400000000
             mpuclk                   1           1            800000000
                smp_twd               1           1            200000000
      Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
      Reviewed-by: NPavel Machek <pavel@denx.de>
      Signed-off-by: NOlof Johansson <olof@lixom.net>
      042000b0
  7. 13 4月, 2013 2 次提交
  8. 12 4月, 2013 5 次提交
  9. 09 4月, 2013 1 次提交
  10. 08 4月, 2013 1 次提交
  11. 05 4月, 2013 3 次提交
  12. 04 4月, 2013 8 次提交
  13. 27 3月, 2013 2 次提交
    • E
      clk: sunxi: rename compatible strings · e3276998
      Emilio López 提交于
      During the introduction of the Allwinner SoC platforms, sunxi was
      initially meant as a generic name for all the variants of the Allwinner
      SoC.
      
      It was ok at the time of the support of only the A10 and A13 that
      look pretty much the same; but it's beginning to be troublesome with
      the future addition of the Allwinner A31 (sun6i) that is quite
      different, and would introduce some weird logic, where sunxi would
      actually mean in some case sun4i and sun5i but without sun6i...
      
      Moreover, it makes the compatible strings naming scheme not consistent
      with other architectures, where usually for this kind of compability, we
      just use the oldest SoC name that has this IP, so let's do just this.
      Signed-off-by: NEmilio López <emilio@elopez.com.ar>
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      e3276998
    • E
      clk: arm: sunxi: Add a new clock driver for sunxi SOCs · e874a669
      Emilio López 提交于
      This commit implements the base CPU clocks for sunxi devices. It has
      been tested using a slightly modified cpufreq driver from the
      linux-sunxi 3.0 tree.
      
      Additionally, document the new bindings introduced by this patch.
      
      Idling:
          / # cat /sys/kernel/debug/clk/clk_summary
             clock                        enable_cnt  prepare_cnt  rate
          ---------------------------------------------------------------------
           osc32k                         0           0            32768
           osc24M_fixed                   0           0            24000000
              osc24M                      0           0            24000000
                 apb1_mux                 0           0            24000000
                    apb1                  0           0            24000000
                 pll1                     0           0            60000000
                    cpu                   0           0            60000000
                       axi                0           0            60000000
                          ahb             0           0            60000000
                             apb0         0           0            30000000
           dummy                          0           0            0
      
      After "yes >/dev/null &":
          / # cat /sys/kernel/debug/clk/clk_summary
             clock                        enable_cnt  prepare_cnt  rate
          ---------------------------------------------------------------------
           osc32k                         0           0            32768
           osc24M_fixed                   0           0            24000000
              osc24M                      0           0            24000000
                 apb1_mux                 0           0            24000000
                    apb1                  0           0            24000000
                 pll1                     0           0            1008000000
                    cpu                   0           0            1008000000
                       axi                0           0            336000000
                          ahb             0           0            168000000
                             apb0         0           0            84000000
           dummy                          0           0            0
      Signed-off-by: NEmilio López <emilio@elopez.com.ar>
      Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
      Signed-off-by: NMike Turquette <mturquette@linaro.org>
      e874a669
  14. 25 3月, 2013 2 次提交