Now that the Blackfin machine drivers have been updated to the
multicomponent support, update the resources to match.  The pin
settings are now a board issue and removed from the driver.
Signed-off-by: NScott Jiang <scott.jiang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since the bfin_write() func needs proper type information in order to
expand into the right bfin_writeX() variant, preserve the addr's type
when setting up the local __addr.  Otherwise the helpers will detect
the variant based upon sizeof(void) which is almost never right.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Use tabs instead of spaces to indent.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The BF537 SIC combines the gpio port H mask A interrupts with the
emac rx interrupt, so we need to demux this in software.

It also combines the gpio port H mask B and the emac tx interrupts,
and the watchdog and port F mask B interrupts, but since we don't
support mask B yet, just add the defines for now.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The SIC interrupt line muxing that the bf537 does is specific to this
CPU (thankfully), so rip it out of the common code and move it to a
bf537-specific file.  This tidies up the common code significantly.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These are only used in a few internal Blackfin places, so move the irq
prototypes out of the global header and into the internal irq one.  No
functional changes other than shuffling locales.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

These are in linux/ptrace.h, so no need for us to duplicate them.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Make sure we mark cache flushing as unsafe to kgdb in SMP mode so that
kgdb doesn't flush things incorrectly on us.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Not sure when we stopped using this field, but nothing in the tree uses
this now, so punt it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since the on-chip L1 regions are not cacheable, there is no point in
trying to flush/invalidate them.  Plus, older Blackfin parts like to
trigger an exception (like BF533-0.3).
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

When suspending/resuming, the common task freezing code will run in
parallel and freeze processes on each core.  This is because the code
uses the non-smp version of memory barriers (as well it should).

The Blackfin smp barrier logic at the moment contains the cache sync
logic, but the non-smp barriers do not.  This is incorrect as Rafel
summarized:
> ...
> The existing memory barriers are SMP barriers too, but they are more
> than _just_ SMP barriers.  At least that's how it is _supposed_ to be
> (eg. rmb() is supposed to be stronger than smp_rmb()).
> ...
> However, looking at the blackfin's definitions of SMP barriers I see
> that it uses extra stuff that should _also_ be used in the definitions
> of the mandatory barriers.
> ...

URL: http://lkml.org/lkml/2011/4/13/11
LKML-Reference: <BANLkTi=F-C-vwX4PGGfbkdTBw3OWL-twfg@mail.gmail.com>
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Fixes generated by 'codespell' and manually reviewed.
Signed-off-by: NLucas De Marchi <lucas.demarchi@profusion.mobi>

The le.h header requires things like test_bit to be declared, so we need
to move its inclusion to after the point where that happens.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

minix bit operations are only used by minix filesystem and useless by
other modules.  Because byte order of inode and block bitmaps is different
on each architecture like below:

m68k:
	big-endian 16bit indexed bitmaps

h8300, microblaze, s390, sparc, m68knommu:
	big-endian 32 or 64bit indexed bitmaps

m32r, mips, sh, xtensa:
	big-endian 32 or 64bit indexed bitmaps for big-endian mode
	little-endian bitmaps for little-endian mode

Others:
	little-endian bitmaps

In order to move minix bit operations from asm/bitops.h to architecture
independent code in minix filesystem, this provides two config options.

CONFIG_MINIX_FS_BIG_ENDIAN_16BIT_INDEXED is only selected by m68k.
CONFIG_MINIX_FS_NATIVE_ENDIAN is selected by the architectures which use
native byte order bitmaps (h8300, microblaze, s390, sparc, m68knommu,
m32r, mips, sh, xtensa).  The architectures which always use little-endian
bitmaps do not select these options.

Finally, we can remove minix bit operations from asm/bitops.h for all
architectures.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Andreas Schwab <schwab@linux-m68k.org>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: Michal Simek <monstr@monstr.eu>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Acked-by: NPaul Mundt <lethal@linux-sh.org>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

As the result of conversions, there are no users of ext2 non-atomic bit
operations except for ext2 filesystem itself.  Now we can put them into
architecture independent code in ext2 filesystem, and remove from
asm/bitops.h for all architectures.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Cc: Jan Kara <jack@suse.cz>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Introduce little-endian bit operations to the big-endian architectures
which do not have native little-endian bit operations and the
little-endian architectures.  (alpha, avr32, blackfin, cris, frv, h8300,
ia64, m32r, mips, mn10300, parisc, sh, sparc, tile, x86, xtensa)

These architectures can just include generic implementation
(asm-generic/bitops/le.h).
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Mikael Starvik <starvik@axis.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Matthew Wilcox <willy@debian.org>
Cc: Grant Grundler <grundler@parisc-linux.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Hirokazu Takata <takata@linux-m32r.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: NHans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: N"H. Peter Anvin" <hpa@zytor.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Hook up name_to_handle_at, open_by_handle_at, and clock_adjtime.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch fixes the Blackfin irqflags to make them I-pipe aware anew,
after the introduction of the hard_local_irq_*() API.
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

This patch introduces Blackfin-specific bits to support the current
tip of the interrupt pipeline development, mainly:

- 2/3-level interrupt maps (sparse IRQs)
- generic virq handling
- sysinfo v2 format for ipipe_get_sysinfo()
Signed-off-by: NPhilippe Gerum <rpm@xenomai.org>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

In order to safely work around anomaly 05000491, we have to execute IFLUSH
from L1 instruction sram.  The trouble with multi-core systems is that all
L1 sram is visible only to the active core.  So we can't just place the
functions into L1 and call it directly.  We need to setup a jump table and
place the entry point in external memory.  This will call the right func
based on the active core.

In the process, convert from the manual relocation of a small bit of code
into Core B's L1 to the more general framework we already have in place
for loading arbitrary pieces of code into L1.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Re-use some of the existing cpu hotplugging code in the process.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The RX lock is used to protect the RX buffer from concurrent access in DMA
mode between the timer and RX interrupt routines.  It is independent from
the uart lock which is used to protect the TX buffer.  It is possible for
a uart TX transfer to be started up from the RX interrupt handler if low
latency is enabled.  So we need to split the locks to avoid deadlocking in
this situation.

In PIO mode, the RX lock is not necessary because the handle_simple_irq
and handle_level_irq functions ensure driver interrupt handlers are called
once on one core.

And now that the RX path has its own lock, the TX interrupt has nothing to
do with the RX path, so disabling it at the same time.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NGreg Kroah-Hartman <gregkh@suse.de>

Any consumer of dpmc.h expects to use VR_CTL, so also pull in the new
mach/pll.h header for those functions.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Since we're breaking apart some inter-header dependencies to avoid more
circular loops, move the blackfin_core_id() definition to the func that
it is based upon.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The SMP code needs "asmlinkage" which linkage.h provides.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Common code expects these to be defined for SMP ports, so add them.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The common asm-generic non-atomic bitops.h defines test_bit() for us, but
we need to use our own version.  So redirect the definition of this func
to avoid having to inline the rest of the asm-generic file.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The external functions are named __raw_xxx, not arch_xxx, so rename the
prototypes to match reality.  This fixes some simple build errors in the
bfin_ksyms.c code which exports these helpers to modules.
Signed-off-by: NGraf Yang <graf.yang@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Rather than maintain Kconfig entries where people have to enter raw
numbers and hardcode lists of addresses/pins in the driver itself,
push it all to platform resources.  This lets us simplify the driver,
the Kconfig, and gives board porters greater flexibility.

In the process, we need to also start supporting the early platform
interface.  Not a big deal, but it causes the patch to be bigger than
a simple resource relocation.

All the Blackfin boards already have their resources updated and in
place for this change.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Acked-by: NGreg Kroah-Hartman <gregkh@suse.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

The array of pointers is never written, so constify it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

A bunch of arches define reads[bwl]/writes[bwl] helpers for accessing
memory mapped registers.  Since the Blackfin ones aren't specific to
Blackfin code, move them to the common asm-generic/io.h for people.
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Each Blackfin port has been duplicating UART structures and defines when
there really is no need for it.  So start a new bfin_serial.h header to
unify all these pieces and give ourselves a fresh start.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Long ago, PT_TRACESYS_OFF and friends were introduced as hard defines to
avoid straight constants in assembler parts of linux m68k.  They are not
used anymore, and were not updated to follow changes in linux kernel.
Remove them.  When similar constants are needed, they are now generated
using asm-offsets.c.
Signed-off-by: NPhilippe De Muyter <phdm@macqel.be>
Acked-by: NMike Frysinger <vapier@gentoo.org>
Acked-by: NGeert Uytterhoeven <geert@linux-m68k.org>
Acked-by: NGreg Ungerer <gerg@uclinux.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

No one uses these MMRs so we didn't notice when the anomaly handling
logic was inverted.
Reported-by: NRobin Getz <robin.getz@analog.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>