- 03 6月, 2015 3 次提交
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由 Yanir Lubetkin 提交于
This fix handles a hardware issue that prevented i219 from working in legacy interrupts mode (IntMode=0) Signed-off-by: NYanir Lubetkin <yanirx.lubetkin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Yanir Lubetkin 提交于
The indication that a descriptor ring flush is required was read from FEXTNVM7 by mistake. It should be read from the PCI config space. Signed-off-by: NYanir Lubetkin <yanirx.lubetkin@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Yanir Lubetkin 提交于
Unit hang may occur if multiple descriptors are available in the rings during reset or runtime suspend. This state can be detected by testing bit 8 in the FEXTNVM7 register. If this bit is set and there are pending descriptors in one of the rings, we must flush them prior to reset. Same applies entering runtime suspend. Signed-off-by: NYanir Lubetkin <yanirx.lubetkin@intel.com> Reviewed-by: NAlexander Duyck <alexander.h.duyck@redhat.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 24 2月, 2015 1 次提交
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由 David Ertman 提交于
i219 is the next-generation LOM that will be available on systems with the Sunrise Point Platform Controller Hub (PCH) chipset from Intel. This patch provides the initial support for the device. Signed-off-by: NDave Ertman <david.m.ertman@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Tested-by: NCarmen Edwards <carmenx.edwards@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 26 7月, 2014 1 次提交
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由 David Ertman 提交于
On I217 and newer hardware, EEE is enabled in the PHY by the software when link is up and disabled by the hardware when link is lost. To enable EEE in Sx (When both ends of the link support, and are enabled for, EEE and 100Mbps), we need to disable LPLU and configure the PHY to automatically enable EEE when link is up, since there will be no software to complete the task. To configure this in the PHY, the Auto Enable LPI bit in the Low Power Idle GPIO Control register must be set. For normal operation in S0, this bit must be cleared. Signed-off-by: NDave Ertman <david.m.ertman@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 06 5月, 2014 2 次提交
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由 David Ertman 提交于
Several customers have reported a link flap issue on 82579. The symptoms are random and intermittent link losses when 82579 is connected to specific link partners. Issue has been root caused as interoperability problem between 82579 and at least some Broadcom PHYs in the Energy Efficient Ethernet wake mechanism. To fix the issue, we are disabling the Phase Locked Loop shutdown in 100M Low Power Idle. This solution will cause an increase of power in 100M EEE link. It will cost additional 28mW in this specific mode. Cc: Lukasz Adamczuk <lukasz.adamczuk@intel.com> Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 David Ertman 提交于
In commit 772d05c5 "e1000e: slow performance between two 82579 connected via 10Mbit hub", a workaround was put into place to address the overaggressive transmit behavior of 82579 parts when connecting at 10Mbs half-duplex. This same behavior is seen on i217 and i218 parts as well. This patch expands the original workaround to encompass these parts. Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 08 3月, 2014 4 次提交
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由 David Ertman 提交于
Previous commit c3a0dce3 fixed an overrun for the RAR on i218 devices. This commit also attempted to homogenize the RAR/SHRA access for all parts accessed by the e1000e driver. This change introduced an error for assigning MAC addresses to guest OS's for 82579 devices. Only RAR[0] is accessible to the driver for 82579 parts, and additional addresses must be placed into the SHRA[L|H] registers. The rar_entry_count was changed in the previous commit to an inaccurate value that accounted for all RAR and SHRA registers, not just the ones usable by the driver. This patch fixes the count to the correct value and adjusts the e1000_rar_set_pch2lan() function to user the correct index. Cc: John Greene <jogreene@redhat.com> Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 David Ertman 提交于
ULP is a power saving feature that reduces the power consumption of the PHY when a cable is not connected. ULP is gated on the following conditions: 1) The hardware must support ULP. Currently this is only I218 devices from Intel 2) ULP is initiated by the driver, so, no driver results in no ULP. 3) ULP's implementation utilizes Runtime Power Management to toggle its execution. ULP is enabled/disabled based on the state of Runtime PM. 4) ULP is not active when wake-on-unicast, multicast or broadcast is active as these features are mutually-exclusive. Since the PHY is in an unavailable state while ULP is active, any access of the PHY registers will fail. This is resolved by utilizing kernel calls that cause the device to exit Runtime PM (e.g. pm_runtime_get_sync) and then, after PHY access is complete, allow the device to resume Runtime PM (e.g. pm_runtime_put_sync). Under certain conditions, toggling the LANPHYPC is necessary to disable ULP mode. Break out existing code to toggle LANPHYPC to a new function to avoid code duplication. Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Cc: Bruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 David Ertman 提交于
This patch is to update the GPL header by removing the portion that refers to the Free Software Foundation address. Change the copyright date for 2014. Reformat the header comments to conform to kernel networking coding norms Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 David Ertman 提交于
Enabling EEE LPI sooner than one second after link up on 82579 causes link issues with some switches. Remove EEE enablement for 82579 parts from the link initialization flow to avoid initializing too early. EEE initialization for 82579 will be done in e1000e_update_phy_task. Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> Acked-by: NBruce W Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 14 9月, 2013 1 次提交
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由 David Ertman 提交于
When copying the MAC RAR registers to PHY there is an error in the calculation of the rar_entry_count, which causes a write of unknown/ undefined register space in the MAC to unknown/undefined register space in the PHY. This patch fixes the overrun with writing to the PHY RAR and also fixes the ethtool offline register tests so that the correctly addressed registers have the appropriate bitmasks for R/W and RO bits for affected parts. Shawn Rader gets credit for finding and fixing the register overrun. Signed-off-by: NDave Ertman <davidx.m.ertman@intel.com> CC: Shawn Rader <shawn.t.rader@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 28 7月, 2013 1 次提交
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由 Bruce Allan 提交于
Tx hang is an unintended consequence of another workaround that is in the EEPROM for an issue with the firmware at 10Mbps when K1 (a power mode of the MAC-PHY interconnect) is enabled. The issue is resolved by setting appropriate Tx re-transmission timeouts in the PHY and associated K1 entry times in the MAC to allow enough transmissions to occur without triggering a Tx hang. A similar change is needed when linked at 10Mbps to improve latency. Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 28 3月, 2013 3 次提交
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由 Bruce Allan 提交于
Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Bruce Allan 提交于
Devices supported by the driver which support EEE (currently 82579, I217 and I218) are advertising EEE capabilities during auto-negotiation even when EEE has been disabled. In addition to not acting as expected, this also caused the EEE status reported by 'ethtool --show-eee' to be wrong when two of these devices are connected back-to-back and EEE is disabled on one. In addition to fixing this issue, the ability for the user to specify which speeds (100 or 1000 full-duplex) to advertise EEE support has been added. Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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由 Bruce Allan 提交于
Two 82579 LOMs connected via a 10Mb hub experience extraordinarily low performance. This is because 82579 is excessively aggressive on transmit at 10Mb half-duplex and will not provide sufficient time for the link partner to transmit. When the link partner is also 82579, the result is a lot of collisions (and corresponding re-transmits) that cause the poor performance. To work-around this issue, significantly increase the IPG in the MAC to allow enough gap for the link partner to transmit and reduce the Rx latency in the analog PHY to 0 to reduce the number of collisions. Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 05 3月, 2013 1 次提交
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由 Bruce Allan 提交于
At 1000Mbps link speed, one of the MAC's internal clocks can be stopped for up to 4us when entering K1 (a power mode of the MAC-PHY interconnect). If the MAC is waiting for completion indications for 2 DMA write requests into Host memory (e.g. descriptor writeback or Rx packet writing) and the indications occur while the clock is stopped, both indications will be missed by the MAC causing the MAC to wait for the completion indications and be unable to generate further DMA write requests. This results in an apparent hardware hang. Work-around the issue by disabling the de-assertion of the clock request when 1000Mbps link is acquired (K1 must be disabled while doing this). Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NJeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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- 05 2月, 2013 1 次提交
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由 Bruce Allan 提交于
Move #defines and function prototypes specific to the ICH/PCH family of devices (ICH8/82562, ICH8/82566, ICH8/82567, ICH9/82562, ICH9/82566, ICH9/82567, ICH10/82567, 82577, 82578, 82579, I217, I218) to the new ich8lan.h header file (the convention for Intel wired ethernet drivers is to use the name of the first device in the family for related file and function names). These defines and function prototypes can be used by other files in the driver and moving them to the ICH/PCH-family-specific file makes it clearer to which devices they are applicable. Signed-off-by: NBruce Allan <bruce.w.allan@intel.com> Tested-by: NAaron Brown <aaron.f.brown@intel.com> Signed-off-by: NJeff Kirsher <jeffrey.t.kirsher@intel.com>
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