1. Qualcom IPQ4019 SoC uses QPIC NAND controller version 1.4.0
   which uses BAM DMA Engine while IPQ806x uses EBI2 NAND
   which uses ADM DMA Engine.
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
   while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
   BAM DMA.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

1. Correct the compatible string for IPQ806x
2. Change the NAND controller and NAND chip nodes name
   for more clarity.
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Currently the compatible “qcom,nandcs” is being used for each
connected NAND device to support for multiple NAND devices in the
same bus. The same thing can be achieved by looking reg property
for each sub nodes which contains the chip select number so this
patch removes the use of “qcom,nandcs” for specifying NAND device
sub nodes.

Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: NAbhishek Sahu <absahu@codeaurora.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Add DT bindings document for the Qualcomm NAND controller driver.
Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NArchit Taneja <architt@codeaurora.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>