- 07 9月, 2012 4 次提交
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由 Ulf Hansson 提交于
Remove machine specific clock implementation and switch to use new common clock framework. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Ulf Hansson 提交于
First version of clock definitions of PRCMU and PRCC clocks for the u8500 platform. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Ulf Hansson 提交于
In this first version of the clock definitions, the structure for ux500 are set. Support for u8500, u9540 and u8540 are prepared. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Ulf Hansson 提交于
First version of common clock implementation of PRCMU clocks and PRCC clocks for ux500 platforms. Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 05 9月, 2012 1 次提交
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由 Linus Walleij 提交于
There is no choice to have the RealView clocks as module for sure, so turn this config option into a boolean. Reported-by: NPawel Moll <pawel.moll@arm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 01 9月, 2012 1 次提交
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由 Kelvin Cheung 提交于
This adds clock support to Loongson1B SoC using the common clock infrastructure. Signed-off-by: NKelvin Cheung <keguang.zhang@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 29 8月, 2012 4 次提交
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由 Chao Xie 提交于
Initialize the clocks for mmp2 Signed-off-by: NChao Xie <xiechao.mail@gmail.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
Initialize the clocks for pxa910 Signed-off-by: NChao Xie <xiechao.mail@gmail.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
Initialize the clocks for pxa168 Signed-off-by: NChao Xie <xiechao.mail@gmail.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Chao Xie 提交于
add mmp specific clocks including apbc cloks, apmu clocks, and pll2, fraction clocks Signed-off-by: NChao Xie <xiechao.mail@gmail.com> Reviewed-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NHaojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 25 8月, 2012 2 次提交
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由 Linus Walleij 提交于
This converts the ARM RealView machine over to using the common clock. The approach is similar to the one used for the Integrator, and we're reusing the ICST wrapper code. We have to put the clock intialization in the timer init function for the clocks to be available when initializing the timer, keeping them in early_init() is too early for the common clk. Since we now have to go down and compile drivers/clk/versatile a CONFIG_COMMON_CLK_VERSATILE symbol has been added so the proper code gets compiled into the kernel for either machine. A leftover CLK_VERSATILE in the Integrator Kconfig was fixed up to use the new symbol as well. Tested on ARM RealView PB1176. Cc: Pawel Moll <pawel.moll@arm.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Barry Song 提交于
Signed-off-by: NBarry Song <Baohua.Song@csr.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 31 7月, 2012 2 次提交
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由 Fengguang Wu 提交于
clk_get() returns -ENOENT on error and some careless caller might dereference it without error checking: In mxc_rnga_remove(): struct clk *clk = clk_get(&pdev->dev, "rng"); // ... clk_disable(clk); Since it's insane to audit the lots of existing and future clk users, let's add a check in the callee to avoid kernel panic and warn about any buggy user. Cc: Russell King <rmk@arm.linux.org.uk> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: viresh kumar <viresh.linux@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Viresh Kumar 提交于
menu "Common Clock Framework" has "depends on COMMON_CLK" and so configs defined within menu don't require these "depends on COMMON_CLK again". Signed-off-by: NViresh Kumar <viresh.kumar@st.com> Cc: Wolfram Sang <w.sang@pengutronix.de> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jeff Garzik <jgarzik@redhat.com> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Bhupesh Sharma <bhupesh.sharma@st.com> Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Mike Turquette <mturquette@linaro.org> Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: viresh kumar <viresh.linux@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 20 7月, 2012 2 次提交
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由 Rob Herring 提交于
With commit 766e6a4e (clk: add DT clock binding support), compiling with OF && !COMMON_CLK is broken. Reported-by: NAlexandre Pereira da Silva <aletes.xgr@gmail.com> Reported-by: NPrashant Gaikwad <pgaikwad@nvidia.com> Signed-off-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Shawn Guo 提交于
The commit 766e6a4e (clk: add DT clock binding support) plugs device tree clk lookup of_clk_get_by_name into clk_get, and fall on non-DT lookup clk_get_sys if DT lookup fails. The return check on of_clk_get_by_name takes (clk != NULL) as a successful DT lookup. But it's not the case. For any system that does not define clk lookup in device tree, ERR_PTR(-ENOENT) will be returned, and consequently, all the client drivers calling clk_get in their probe functions will fail to probe with error code -ENOENT returned. Fix the issue by checking of_clk_get_by_name return with !IS_ERR(clk), and update of_clk_get and of_clk_get_by_name for !CONFIG_OF build correspondingly. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NRob Herring <rob.herring@calxeda.com> Tested-by: NMarek Vasut <marex@denx.de> Tested-by: NLauri Hintsala <lauri.hintsala@bluegiga.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 19 7月, 2012 1 次提交
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由 Dinh Nguyen 提交于
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Reviewed-by: NPavel Machek <pavel@denx.de> Reviewed-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: NArnd Bergmann <arnd@arndb.de>
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- 18 7月, 2012 6 次提交
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由 Vipul Kumar Samar 提交于
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl register bit no. 23:25, with following possibilities 0XX: pll1_clk 10X: sys_synth_clk 110: pll2_clk 111: pll3_clk Out of several possibilities (h/w wise) to select same clock parent for sys_clk, current clock implementation was considering just one value. When bootloader programmed different (valid) value to select a clock parent then Linux breaks. Here, we try to include all possibilities which can lead to same clock selection thus making Linux independent of bootloader selection values. Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
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由 Vipul Kumar Samar 提交于
This patch is to fix typing mistake of clk enable register of i2c1 and uart1. Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
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由 Vipul Kumar Samar 提交于
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk pll3_48m -> pll3_ Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 Vipul Kumar Samar 提交于
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk ras_gen1_synth_gate_clk -> ras_syn1_gclk ras_pll3_48m -> ras_pll3_ pll3_48m -> pll3_ Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 Vipul Kumar Samar 提交于
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many clk ids are exceeding this predefined limit. This patch is intended to rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad -> gmii_pad Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 Vipul Kumar Samar 提交于
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many clk ids are exceeding this predefined limit. This patch rename clk ids like: mux_clk -> _mclk gate_clk -> _gclk synth_clk -> syn_clk gmac_phy -> phy_ gmii_125m_pad_ -> gmii_pad Signed-off-by: NVipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: NShiraz Hashim <shiraz.hashim@st.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 12 7月, 2012 12 次提交
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由 Richard Zhao 提交于
Signed-off-by: NRichard Zhao <richard.zhao@freescale.com> Tested-by: NSubodh Nijsure <snijsure@grid-net.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Rob Herring 提交于
This adds real clock support to Calxeda Highbank SOC using the common clock infrastructure. Signed-off-by: NRob Herring <rob.herring@calxeda.com> [mturquette@linaro.org: fixed up invalid writes to const struct member] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Grant Likely 提交于
Add support for DT "fixed-clock" binding to the common fixed rate clock support. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> [Rob Herring] Rework and move into common clock infrastructure Signed-off-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Grant Likely 提交于
Based on work 1st by Ben Herrenschmidt and Jeremy Kerr, then by Grant Likely, this patch adds support to clk_get to allow drivers to retrieve clock data from the device tree. Platforms scan for clocks in DT with of_clk_init and a match table, and the register a provider through of_clk_add_provider. The provider's clk_src_get function will be called when a device references the provider's OF node for a clock reference. v6 (Rob Herring): - Return error values instead of NULL to match clock framework expectations v5 (Rob Herring): - Move from drivers/of into common clock subsystem - Squashed "dt/clock: add a simple provider get function" and "dt/clock: add function to get parent clock name" - Rebase to 3.4-rc1 - Drop CONFIG_OF_CLOCK and just use CONFIG_OF - Add missing EXPORT_SYMBOL to various functions - s/clock-output-name/clock-output-names/ - Define that fixed-clock binding is a single output v4 (Rob Herring): - Rework for common clk subsystem - Add of_clk_get_parent_name function v3: - Clarified documentation v2: - fixed errant ';' causing compile error - Editorial fixes from Shawn Guo - merged in adding lookup to clkdev - changed property names to match established convention. After working with the binding a bit it really made more sense to follow the lead of 'reg', 'gpios' and 'interrupts' by making the input simply 'clocks' & 'clock-names' instead of 'clock-input-*', and to only use clock-output* for the producer nodes. (Sorry Shawn, this will mean you need to change some code, but it should be trivial) - Add ability to inherit clocks from parent nodes by using an empty 'clock-ranges' property. Useful for busses. I could use some feedback on the new property name, 'clock-ranges' doesn't feel right to me. Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NShawn Guo <shawn.guo@freescale.com> Cc: Sascha Hauer <kernel@pengutronix.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Linus Walleij 提交于
This converts the Integrator platform to use common clock and the ICST driver. Since from this point not all ARM reference platforms use the clock, we define CONFIG_PLAT_VERSATILE_CLOCK and select it for all platforms except the Integrator. Open issue: I could not use the .init_early() field of the machine descriptor to initialize the clocks, but had to move them to .init_irq(), so presumably .init_early() is so early that common clock is not up, and .init_machine() is too late since it's needed for the clockevent/clocksource initialization. Any suggestions on how to solve this is very welcome. Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: use 'select' instead of versatile Kconfig] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Linus Walleij 提交于
The ICST307 VCO clock has a shared driver in the ARM architecture. This patch provides a wrapper into the common clock framework so we can use the implementation in the ARM architecture without duplicating the code until all ARM platforms using this VCO are moved over. At that point we can merge the driver from the ARM platform into the generic file altogether. Cc: Russell King <linux@arm.linux.org.uk> Cc: Mike Turquette <mturquette@ti.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: removed versatile Kconfig] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Linus Walleij 提交于
This converts the U300 clock implementation over to use the common struct clk and moves the implementation down into drivers/clk. Since VCO isn't used in tree it was removed, it's not hard to put it back in if need be. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> [mturquette@linaro.org: trivial Makefile conflict] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rajendra Nayak 提交于
caching parent clocks makes sense only when a clock has more than one parent (mux clocks). Avoid doing this for every other clock. Signed-off-by: NRajendra Nayak <rnayak@ti.com> [mturquette@linaro.org: removed extra parentheses] Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mark Brown 提交于
The WM831x and WM832x series of PMICs contain a flexible clocking subsystem intended to provide always on and system core clocks. It features: - A 32.768kHz crystal oscillator which can optionally be used to pass through an externally generated clock. - A FLL which can be clocked from either the 32.768kHz oscillator or the CLKIN pin. - A CLKOUT pin which can bring out either the oscillator or the FLL output. - The 32.768kHz clock can also optionally be brought out on the GPIO pins of the device. This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL is supported only in AUTO mode, the full flexibility of the FLL cannot currently be used. Due to a lack of access to systems where the core SoC has been converted to use the generic clock API this driver has been compile tested only. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rajendra Nayak 提交于
Most platforms end up using a mix of basic clock types and some which use clk_hw_foo struct for filling in custom platform information when the clocks don't fit into basic types supported. In platform code, its useful to know if a clock is using a basic type or clk_hw_foo, which helps platforms know if they can safely use to_clk_hw_foo to derive the clk_hw_foo pointer from clk_hw. Mark all basic clocks with a CLK_IS_BASIC flag. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rajendra Nayak 提交于
Some divider clks do not have any obvious relationship between the divider and the value programmed in the register. For instance, say a value of 1 could signify divide by 6 and a value of 2 could signify divide by 4 etc. Also there are dividers where not all values possible based on the bitfield width are valid. For instance a 3 bit wide bitfield can be used to program a value from 0 to 7. However its possible that only 0 to 4 are valid values. All these cases need the platform code to pass a simple table of divider/value tuple, so the framework knows the exact value to be written based on the divider calculation and can also do better error checking. This patch adds support for such rate table based dividers and as part of the support adds a new registration function 'clk_register_divider_table()' and a new macro for static definition 'DEFINE_CLK_DIVIDER_TABLE'. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Rajendra Nayak 提交于
Quite often dividers and the value programmed in the register have a relation of 'power of two', something like value div 0 1 1 2 2 4 3 8... Add support for such dividers as part of clk-divider. The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used to define such clocks. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 05 7月, 2012 1 次提交
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由 Lauri Hintsala 提交于
SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand the frequency fix for ref_io1 to get SSP2 and SSP3 to work. Signed-off-by: NLauri Hintsala <lauri.hintsala@bluegiga.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 04 7月, 2012 1 次提交
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由 Rajendra Nayak 提交于
The below commit introduced a bug in __clk_set_parent() which could cause it to *skip* the parent validation which makes sure the parent passed to the api is a valid one. commit 7975059d Author: Rajendra Nayak <rnayak@ti.com> Date: Wed Jun 6 14:41:31 2012 +0530 clk: Allow late cache allocation for clk->parents This was identified by the following compiler warning.. drivers/clk/clk.c: In function '__clk_set_parent': drivers/clk/clk.c:1083:5: warning: 'i' may be used uninitialized in this function [-Wuninitialized] .. as reported by Marc Kleine-Budde. There were various options discussed on how to fix this, one being initing 'i' to clk->num_parents, but the below approach was found to be more appropriate as it also makes the 'parent validation' code simpler to read. Reported-by: NMarc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org> Cc: stable@kernel.org
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- 27 6月, 2012 3 次提交
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由 Shawn Guo 提交于
Add pwm clock lookup for imx23 and imx28 booting from device tree. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
The correct name for the GPMI clock is 'gpmi-nand'. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Huang Shijie 提交于
rename the clock name from `8000c000.gpmi` to `8000c000.gpmi-nand`. Signed-off-by: NHuang Shijie <b32955@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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