sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum
CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise
the voltage for the lowest operating point to 1.0 volts in order to stay
within the SoC specifications. It is an undervolted setting that isn't
stable across all SoCs and boards out there.

Cc: <stable@vger.kernel.org> # v4.0+
Fixes: d96b7161 ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi")
Signed-off-by: NTimo Sigurdsson <public_timo.s@silentcreek.de>
Acked-by: NIain Paton <ipaton0@gmail.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Tim Bird <tim.bird@sonymobile.com>
Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Mathieu Olivari <mathieu@codeaurora.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use stdout-path so that we don't have to put the console on the
kernel command line.

Cc: Mike Rapoport <mike.rapoport@gmail.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add a label to the serial nodes that are being used for the
console.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

rtc can either be supplied from internal 32k clock or external crystal
generated 32k clock. Internal clock is SOC specific and the external
clock is board dependent. Adding the corresponding nodes.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>

Since the LED modes mapping is no longer hardcoded inside the leds-ns2
driver, then it must be provided through the modes-map property in the
ns2-leds nodes.
Signed-off-by: NVincent Donnefort <vdonnefort@gmail.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJacek Anaszewski <j.anaszewski@samsung.com>

The base addresses for the Ux500 PRCC controllers are hardcoded,
let's move them to the clock node in the device tree and delete
the constants.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is
explicit.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Current base address is wrong by 0x04 bytes for AHB bus device as shown
in dmesg:

	tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround

To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb:
detect and correct bogus base address") checks for the low bit of the
base address and removes theses 0x04 bytes at runtime.

This patch fixes the original DTS, so upstream version doesn't need the
workaround of the base address.

As both addresses are valid, this patch doesn't break compatibility.

Tested on tegra20-paz00 (aka ac100).
Signed-off-by: NNicolas Chauvet <kwizart@gmail.com>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

This patch modifies the device tree for Tegra124 based devices to enable
the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1
TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1.
Signed-off-by: NKyle Huey <khuey@kylehuey.com>
Acked-by: NMark Rutland <mark.rutland@arm.com>
Acked-by: NJon Hunter <jonathanh@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the device-tree node for the GK20A GPU and leave it disabled.
It is the responsibility of the bootloader to enable it if the
VPR registers have been programmed such that the GPU can operate.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>

Nouveau can make use of the IOMMU to make physical appear linear in the
GPU address space.
Signed-off-by: NAlexandre Courbot <acourbot@nvidia.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Specify the CPU voltage regulator for the cpufreq driver.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The Tegra124 cpufreq driver relies on certain clocks being present
in the /cpus/cpu@0 node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

The DFLL clocksource is a separate IP block from the usual
clock-and-reset controller, so it gets its own device tree node.
Signed-off-by: NTuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: NMikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: NMichael Turquette <mturquette@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This SoC is integrated with 4 Cortex-A9 cores.  The GIC bindings
document says that the bits[15:8] of the 3rd cell of the interrupts
property represents PPI interrupt CPU mask.  Because the timer
interrupts are wired to all of the 4 cores, bits[15:8] should be set
to 0xf.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

When getting translated from a downstream device tree that used slightly
different DT bindings, these regulators got labeled with the
"on-in-suspend" state, when they were actually supposed to be turned off
for S3 suspend. This was harmless, but not intentional, AFAICT.

Let's turn them off to get the optimal power state.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

This DTS file was submitted with non-upstream bindings. I happened
across this while reviewing the jaq DTS.
Signed-off-by: NBrian Norris <briannorris@chromium.org>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>

The sp810 clk driver is calling the clk consumer APIs from
clk_prepare ops to change the parent to a 1 MHz fixed rate clock
for each of the clocks that the driver provides. Use
assigned-clock-parents for this instead of doing it in the driver
to avoid using the consumer API in provider code. This also
allows us to remove the usage of clk provider APIs that take a
struct clk as an argument from the sp810 driver.

Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Tested-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NOlof Johansson <olof@lixom.net>

There are some missing dependencies at the DT, as it looks for
an I2C bus named "ssc2", but this is not defined.

Probably, it misses some dependencies from some other tree.
For now, revert this patch, to avoid build breakages.

This reverts commit 5d8877b6.
Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>

This change is a code reorganization. Here we introduce
serial_imx_enable_wakeup() helper function to do
the job of configuring and preparing wakeup sources
on imx serial device. The idea is to allow other
parts of the code to call this function whenever
the device is known to go to idle.

Cc: Fabio Estevam <festevam@gmail.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.com>
Cc: linux-serial@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

CPSW driver has been updated with compatibles for enabling errata
workarounds. So updating cpsw compatibles.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

JPEG codec node has been added in parallel to the patch, which
added support for IOMMU to Exynos platform, so JPEG device for
Exynos4 SoCs lacked IOMMU property. This patch fixes this issue.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

SPI1 is available on IO Port #2 (as depicted on their website)
in PCB Revision 0.5 of Hardkernel Odroid U3 board.
The shield connects a 256KiB spi-nor flash on that bus.
Signed-off-by: NAlexis Ballier <aballier@gentoo.org>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

Although there is only one choice of chipselect it is necessary to
specify it. The driver cannot claim the gpio otherwise.
Signed-off-by: NMichal Suchanek <hramrach@gmail.com>
Acked-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch add the cooling device to control the overheating issue on
Exynos3250-based Rinato/Monk board.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

The odroid-xu3 board which is based on exynos5422 not exynos5800
is booted from cortex-a7 core unlike exynos5800. The odroid-xu3's
cpu order is quite strange. cpu0 and cpu5-7 are cortex-a7 cores and
cpu1-4 are cortex-a15 cores. To correct this mis-odering, I added
exynos5422-cpus.dtsi and reversing cpu orders from exynos5420.
Now, cpu0-3 are cortex-a7 and cpu4-7 are cortex-a15.
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NChanho Park <parkch98@gmail.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

For Exynos4x12 platforms, add CPU operating points (using
opp-v2 bindings) and CPU regulator supply properties for
migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.

Based on the earlier work by Thomas Abraham.

Cc: Doug Anderson <dianders@chromium.org>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: NJavier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Tested-by: NTobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Tested-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>

This patch add CPU operating points which include CPU frequency and
regulator voltage to use generic cpufreq drivers.
Signed-off-by: NChanwoo Choi <cw00.choi@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: NBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: NKukjin Kim <kgene@kernel.org>