Requested by arm-soc maintainer Kevin Hilman in v9 review.
http://article.gmane.org/gmane.linux.ports.arm.kernel/456331Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The change adds COMMON_CLK_NXP configuration symbol and enables it for
NXP LPC18XX architecture, this is needed to reuse drivers/clk/nxp
folder for NXP common clock framework drivers other than LPC18XX one.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Acked-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Add a new R-Car H3 Clock Pulse Generator / Module Standby and Software
Reset driver, using the new CPG/MSSR driver core.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CS2000 Fractional-N driver as clock provider.
Signed-off-by: NKuninori Morimoto <kuninori.morimoto.gx@renesas.com>
[sboyd@codeaurora.org: Fix unsigned checked for < 0 in
cs2000_ratio_get()]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Provide support for Sigma Designs Tango4 clock generator.
NOTE: This driver is incompatible with Tango3 clkgen.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
[sboyd@codeaurora.org: Add kernel.h include for panic/sprintf]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The Broadcom Northstar 2 SoC is architected under the iProc
architecture. It has the following PLLs: GENPLL SCR, GENPLL SW,
LCPLL DDR, LCPLL Ports, all derived from an onboard crystal.
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some clocks are using a multiplier component, however, unlike their mux,
gate or divider counterpart, these factors don't have a basic clock
implementation.

This leads to code duplication across platforms that want to use that kind
of clocks, and the impossibility to use the composite clocks with such a
clock without defining your own rate operations.

Create such a driver in order to remove these issues, and hopefully factor
the implementations, reducing code size across platforms and consolidating
the various implementations.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NChen-Yu Tsai <wens@csie.org>

This patch adds the driver and devicetree documentation for the
Silicon Labs SI514 clock generator chip. This is an I2C controlled
oscillator capable of generating clock signals ranging from 100kHz
to 250MHz.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
[sboyd@codeaurora.org: Drop clk.h include, remove some casts]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk-bcm2835.c predates the drivers under bcm/, but all the new BCM
drivers are going in there so let's follow them.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org

The file clk-gpio-gate.c does not only contain the gate clock, but also
the mux clock. Rename the file to clk-gpio.c.

Cc: Jyri Sarha <jsarha@ti.com>
Signed-off-by: NSergej Sawazki <ce3a@gmx.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NYoshinori Sato <ysato@users.sourceforge.jp>

The driver supports decoding and statically modelling PLL state (i.e.
we inherit state from bootloader) and provides support for all
peripherals that support simple one-bit gated clocks. The covers all
peripherals whose clocks come from the AHB, APB1 or APB2 buses.

It has been tested on an STM32F429I-Discovery board. The clock counts
for TIM2, USART1 and SYSTICK are all set correctly and the wall clock
looks OK when checked with a stopwatch. I have also tested a prototype
driver for the RNG hardware. The RNG clock is correctly enabled by the
framework (also did inverse test and proved that by changing DT to
configure the wrong clock bit then we observe the RNG driver to fail).
Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org>
Reviewed-by: NMaxime Coquelin <mcoquelin.stm32@gmail.com>
[sboyd@codeaurora.org: Silence sparse warnings]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.

[ralf@linux-mips.org: Resolve a number of simple conflicts.]
Signed-off-by: NHuacai Chen <chenhc@lemote.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/9790/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This driver supports the CGU clocks for Ingenic SoCs. It is generic
enough to be usable across at least the JZ4740 to the JZ4780, and will
be made use of on such devices in subsequent commits. This patch by
itself only adds the SoC-agnostic infrastructure that forms the bulk of
the CGU driver for the aforementioned further commits to make use of.
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Co-authored-by: NPaul Cercueil <paul@crapouillou.net>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10150/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Add driver for NXP LPC18xx/43xx Clock Generation Unit (CGU). The CGU
contains several clock generators and output stages that route the
clocks either directly to peripherals or to a Clock Control Unit
(CCU).
Signed-off-by: NJoachim Eastwood <manabian@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The clock code under drivers/clk/bcm now contains code for both the
Broadcom mobile SoCs and the iProc SoCs. Change the the makefile
dependency to be under config flag CONFIG_ARCH_BCM that's enabled for
both families of SoCs
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

It adds a clock driver for zx296702 SoC to register the clock tree to
Common Clock Framework.  All the clocks of bus topology and some the
peripheral clocks are ready with this commit. Some missing leaf clocks
for peripherals will be added later when needed.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKevin Hilman <khilman@linaro.org>

This patchset adds the infrastructure for registering and managing the
core clocks found on Amlogic MesonX SoCs. In particular:

- PLLs
- CPU clock
- Fixed rate clocks, fixed factor clocks, ...
Signed-off-by: NCarlo Caione <carlo@endlessm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
  Y1 is derived from the input clock
  Y2 and Y3 derive from PLL1
  Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NBintian Wang <bintian.wang@huawei.com>
Acked-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: NZhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: NWill Deacon <will.deacon@arm.com>
Tested-by: NTyler Baker <tyler.baker@linaro.org>
Tested-by: NKevin Hilman <khilman@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

After the cleanup on clock drivers, they are now ready to be moved into
drivers/clk.  Let's move them into drivers/clk/imx folder.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>

This patch adds common clock support for Mediatek SoCs, including plls,
muxes and clock gates.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: NHenry Chen <henryc.chen@mediatek.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
[sboyd@codeaurora.org: Squelch checkpatch warning in clk-mtk.h]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Some board designers, when running out of clock output pads, decide to
(mis)use PWM output pads to provide a clock to external components.
This driver supports this practice by providing an adapter between the
PWM and clock bindings in the device tree. As the PWM bindings specify
the period in the device tree, this is a fixed clock.
Tested-by: NJanusz Uzycki <j.uzycki@elproma.com.pl>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

 The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: NAndy Green <andy.green@linaro.org>
Signed-off-by: NVincent Yang <vincent.yang@socionext.com>
Signed-off-by: NTetsuya Nuriya <nuriya.tetsuya@socionext.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Add helpers for registering clocks and clock providers on Pistachio.
Signed-off-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: devicetree@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Patchwork: https://patchwork.linux-mips.org/patch/9318/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Provide CLK support for Alphascale ASM9260 SoC.
Signed-off-by: NOleksij Rempel <linux@rempel-privat.de>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.
Signed-off-by: NMax Filippov <jcmvbkbc@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@linaro.org>

This is the initial version of the RK808 PMIC.  This is a power management
IC for multimedia products.  It provides regulators that are able to
supply power to processor cores and other components.  The chip provides
other modules including RTC, Clockout.
Signed-off-by: NChris Zhong <zyw@rock-chips.com>
Reviewed-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Samuel Ortiz <sameo@linux.intel.com> says:
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Olof Johansson <olof@lixom.net>
Cc: Dmitry Torokhov <dtor@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Li Zhong <zhong@linux.vnet.ibm.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

Fix the building of pxa clock drivers so that the files are actually
compiled if and only if COMMON_CLK was selected by the architecture.

This prevents conflicts with mach-pxa clock legacy implementation.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add a the common code used by all PXA variants.

This is the first step in the transition from architecture defined
clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to
have the same features (and not all the features) of the existing
clocks, and enable the transition of PXA to device-tree.

All PXA rely on a "CKEN" type clock, which :
 - has a gate (bit in CKEN register)
 - is generated from a PLL, generally divided
 - has an alternate low power clock

Each variant will specialize the CKEN clock :
 - pxa25x have no low power clock
 - pxa27x in low power use always the 13 MHz ring oscillator
 - pxa3xx in low power have specific dividers for each clock

The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get
a handle on the clock. While pxa-clock.h will describe all the clocks of
all the variants, each variant will only use a subset of it.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.
Signed-off-by: NJyri Sarha <jsarha@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to consolidate code
and avoid duplication.
Signed-off-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This adds the clock driver for Cirrus Logic CLPS711X series SoCs
using common clock infrastructure.
Designed primarily for migration CLPS711X subarch for multiplatform & DT,
for this as the "OF" and "non-OF" calls implemented.
Signed-off-by: NAlexander Shiyan <shc_work@mail.ru>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds helper functions to configure clock parents and rates
as specified through 'assigned-clock-parents', 'assigned-clock-rates'
DT properties for a clock provider or clock consumer device.
The helpers are now being called by the bus code for the platform, I2C
and SPI busses, before the driver probing and also in the clock core
after registration of a clock provider.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Palmas class of devices can provide 32K clock(s) to be used by other devices
on the board. Depending on the actual device the provided clocks can be:
CLK32K_KG and CLK32K_KGAUDIO
or only one:
CLK32K_KG (TPS659039 for example)

Use separate compatible flags for the two 32K clock.
A system which needs or have only one of the 32k clock from
Palmas will need to add node(s) for each clock as separate section
in the dts file.
The two compatible property is:
"ti,palmas-clk32kg" for clk32kg clock
"ti,palmas-clk32kgaudio" for clk32kgaudio clock

Apart from the register control of the clocks - which is done via
the clock API there is a posibility to enable the external sleep
control. In this way the clock can be enabled/disabled on demand by the
user of the clock.

See the documentation for more details.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Reviewed-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This is a driver for the AVPLLs built upon a VCO with 8 channels each
found on Marvell Berlin2 SoCs. While both VCOs found on BG2/BG2CD share
the same register set, sometimes registers shifts for one of the VCOs
are a bit off. Nothing serious that should require a separate driver,
so deal with both VCOs in a single driver instead.
Signed-off-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add clk driver to support clock blocks found on the AXM55xx devices. The driver
provides clock implementations for three different types of clock devices on
the AXM55xx device: PLL clock, a clock divider and a clock mux.
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>