1. 12 10月, 2013 3 次提交
  2. 10 10月, 2013 6 次提交
    • M
      can: at91-can: fix device to driver data mapping for platform devices · 5abbeea5
      Marc Kleine-Budde 提交于
      In commit:
      
          3078cde7 can: at91_can: add dt support
      
      device tree support was added to the at91_can driver. In this commit the
      mapping of device to driver data was mixed up. This results in the sam9x5
      parameters being used for the sam9263 and the workaround for the broken mailbox
      0 on the sam9263 not being activated.
      
      This patch fixes the broken platform_device_id table.
      
      Cc: linux-stable <stable@vger.kernel.org>
      Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      5abbeea5
    • M
      can: flexcan: fix mx28 detection by rearanging OF match table · e3587842
      Marc Kleine-Budde 提交于
      The current implemetation of of_match_device() relies that the of_device_id
      table in the driver is sorted from most specific to least specific compatible.
      
      Without this patch the mx28 is detected as the less specific p1010. This leads
      to a p1010 specific workaround is activated on the mx28, which is not needed.
      
      Cc: linux-stable <stable@vger.kernel.org>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      e3587842
    • M
      can: flexcan: flexcan_chip_start: fix regression, mark one MB for TX and abort pending TX · d5a7b406
      Marc Kleine-Budde 提交于
      In patch
      
          0d1862ea can: flexcan: fix flexcan_chip_start() on imx6
      
      the loop in flexcan_chip_start() that iterates over all mailboxes after the
      soft reset of the CAN core was removed. This loop put all mailboxes (even the
      ones marked as reserved 1...7) into EMPTY/INACTIVE mode. On mailboxes 8...63,
      this aborts any pending TX messages.
      
      After a cold boot there is random garbage in the mailboxes, which leads to
      spontaneous transmit of CAN frames during first activation. Further if the
      interface was disabled with a pending message (usually due to an error
      condition on the CAN bus), this message is retransmitted after enabling the
      interface again.
      
      This patch fixes the regression by:
      1) Limiting the maximum number of used mailboxes to 8, 0...7 are used by the RX
      FIFO, 8 is used by TX.
      2) Marking the TX mailbox as EMPTY/INACTIVE, so that any pending TX of that
      mailbox is aborted.
      
      Cc: linux-stable <stable@vger.kernel.org>
      Cc: Lothar Waßmann <LW@KARO-electronics.de>
      Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
      d5a7b406
    • C
      gianfar: Enable eTSEC-20 erratum w/a for P2020 Rev1 · 53fad773
      Claudiu Manoil 提交于
      Enable workaround for P2020/P2010 erratum eTSEC 20,
      "Excess delays when transmitting TOE=1 large frames".
      The impact is that frames lager than 2500-bytes for which
      TOE (i.e. TCP/IP hw accelerations like Tx csum) is enabled
      may see excess delay before start of transmission.
      This erratum was fixed in Rev 2.0.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      53fad773
    • C
      gianfar: Use mpc85xx support for errata detection · 2969b1f7
      Claudiu Manoil 提交于
      Use the macros and defines from mpc85xx.h to simplify
      and prevent errors in identifying a mpc85xx based SoC
      for errata detection.
      This should help enabling (and identifying) workarounds
      for various mpc85xx based chips and revisions.
      For instance, express MPC8548 Rev.2 as:
      (SVR_SOC_VER(svr) == SVR_8548) && (SVR_REV(svr) == 0x20)
      instead of:
      (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020)
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2969b1f7
    • C
      gianfar: Enable eTSEC-A002 erratum w/a for all parts · ad3660c2
      Claudiu Manoil 提交于
      A002 is still in "no plans to fix" state, and applies to all
      the current P1/P2 parts as well, so it's resonable to enable
      its workaround by default, for all the soc's with etsec.
      The impact of not enabling this workaround for affected parts
      is that under certain conditons (runt frames or even frames
      with RX error detected at PHY level) during controller reset,
      the controller might fail to indicate Rx reset (GRS) completion.
      Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      ad3660c2
  3. 09 10月, 2013 10 次提交
  4. 08 10月, 2013 6 次提交
  5. 05 10月, 2013 5 次提交
  6. 03 10月, 2013 7 次提交
  7. 02 10月, 2013 3 次提交