1. 12 1月, 2006 1 次提交
    • A
      [PATCH] x86_64: Generalize DMI and enable for x86-64 · e9928674
      Andi Kleen 提交于
      Some people need it now on 64bit so reuse the i386 code for
      x86-64. This will be also useful for future bug workarounds.
      
      It is a bit simplified there because there is no need
      to do it very early on x86-64. This means it doesn't need
      early ioremap et.al. We run it as a core initcall right now.
      
      I hope it's not needed for early setup.
      
      I added a general CONFIG_DMI symbol in case IA64 or someone
      else wants to reuse the code later too.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      e9928674
  2. 11 1月, 2006 1 次提交
  3. 15 11月, 2005 1 次提交
    • J
      [PATCH] x86_64: Support for AMD specific MCE Threshold. · 89b831ef
      Jacob Shin 提交于
      MC4_MISC - DRAM Errors Threshold Register realized under AMD K8 Rev F.
      This register is used to count correctable and uncorrectable ECC errors that occur during DRAM read operations.
      The user may interface through sysfs files in order to change the threshold configuration.
      
      bank%d/error_count - reads current error count, write to clear.
      bank%d/interrupt_enable - set/clear interrupt enable.
      bank%d/threshold_limit - read/write the threshold limit.
      
      APIC vector 0xF9 in hw_irq.h.
      5 software defined bank ids in mce.h.
      new apic.c function to setup threshold apic lvt.
      defaults to interrupt off, count enabled, and threshold limit max.
      sysfs interface created on /sys/devices/system/threshold.
      
      AK: added some ifdefs to make it compile on UP
      Signed-off-by: NJacob Shin <jacob.shin@amd.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      89b831ef
  4. 30 9月, 2005 1 次提交
  5. 13 9月, 2005 1 次提交
  6. 05 9月, 2005 2 次提交
  7. 25 8月, 2005 1 次提交
  8. 26 6月, 2005 1 次提交
  9. 17 5月, 2005 1 次提交
    • A
      [PATCH] x86_64: Add pmtimer support · 312df5f1
      Andi Kleen 提交于
      There are unfortunately more and more multi processor Opteron systems which
      don't have HPET timer support in the southbridge.  This covers in particular
      Nvidia and VIA chipsets.  They also don't guarantee that the TSCs are
      synchronized between CPUs; and especially with MP powernow the systems are
      nearly unusable because the time gets very inconsistent between CPUs.
      
      The timer code for x86-64 was originally written under the assumption that we
      could fall back to the HPET timer on such systems.  But this doesn't work
      there.
      
      Another alternative is to use the ACPI PM timer as primary time source.  This
      patch does that.  The kernel only uses PM timer when there is no other choice
      because it has some disadvantages.
      
      Ported over from i386.  It should be faster than the i386 version because I
      dropped the "read three times" workaround, but is still considerable slower
      than HPET and also does not work together with vsyscalls which have to be
      disabled.
      
      Cc: <mark.langsdorf@amd.com>
      Signed-off-by: NAndi Kleen <ak@suse.de>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      312df5f1
  10. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4