- 19 2月, 2014 1 次提交
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由 Sergei Shtylyov 提交于
This patch is an attempt to gather the Ethernet related bindings in one file, like it's done in the MMC and some other subsystems. It should save some of the trouble of documenting several properties over and over in each binding document, instead only making reference to the main file. I have used the Embedded Power Architecture(TM) Platform Requirements (ePAPR) standard as a base for the properties description, also documenting some ad-hoc properties that have been introduced over time despite having direct analogs in ePAPR. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 17 2月, 2014 1 次提交
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由 Florian Fainelli 提交于
Document the required "clocks" phandles and their corresponding "clock-names" properties for the two clocks used by the GENET hardware block ("enet" and "enet-wol"). CC: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 2月, 2014 1 次提交
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由 Florian Fainelli 提交于
This patch adds the Device Tree bindings for the Broadcom GENET Gigabit Ethernet controller. A bunch of examples are provided to illustrate the versatile aspect of the hardare. Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 07 2月, 2014 2 次提交
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由 Maxime Ripard 提交于
The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the mdio driver for consistency, and keep the older one for backward compatibility. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Maxime Ripard 提交于
The Allwinner A10 compatibles were following a slightly different compatible patterns than the rest of the SoCs for historical reasons. Add compatibles matching the other pattern to the ethernet driver for consistency, and keep the older one for backward compatibility. Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 2月, 2014 1 次提交
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由 Florian Vaussard 提交于
Add the reg-io-width property to describe the width of the memory accesses. Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: devicetree@vger.kernel.org Acked-by: NRob Herring <robh@kernel.org> Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Tested-by: NAndreas Larsson <andreas@gaisler.com> Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de>
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- 29 1月, 2014 7 次提交
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由 Sergei Shtylyov 提交于
The "ti,davinci-no-bd-ram" property for the DaVinci EMAC binding simply can't be required one, as it's boolean (which means it's absent if false). While at it, document the property better... Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Sergei Shtylyov 提交于
Though described as required, the "ti,davinci-rmii-en" property for the DaVinci EMAC binding seems actually optional, as the driver should happily work without it; the property is not specified either in the example device node or in the actual EMAC device node for DA850 device tree, only AM3517 one. While at it, document the property better... Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Boris BREZILLON 提交于
Add new at91sam9 watchdog properties to the documentation. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Acked-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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由 Leela Krishna Amudala 提交于
Add device tree support for exynos5250 and 5420 SoCs and use syscon regmap interface to configure AUTOMATIC_WDT_RESET_DISABLE and MASK_WDT_RESET_REQUEST registers of PMU to mask/unmask enable/disable of watchdog in probe and s2r scenarios. Signed-off-by: NLeela Krishna Amudala <l.krishna@samsung.com> Signed-off-by: NDoug Anderson <dianders@chromium.org> Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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由 Alexander Shiyan 提交于
This patch adds a watchdog driver for devices controlled through GPIO, (Analog Devices ADM706, Maxim MAX823, National NE555 etc). Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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由 Ivan Khoronzhuk 提交于
The keystone arch uses the same IP watchdog, so add "ti,keystone-wdt" compatible and correct identity. The Keystone arch is using clocks in DT and source clock for watchdog has to be specified, so add this to binding. Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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由 Ivan Khoronzhuk 提交于
Since Davinci WDT has been switched to use WDT core, it became able to support timeout-sec property, so add it to it's binding description. Signed-off-by: NIvan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: NGuenter Roeck <linux@roeck-us.net> Signed-off-by: NWim Van Sebroeck <wim@iguana.be>
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- 28 1月, 2014 1 次提交
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由 NeilBrown 提交于
The 7 lines driven by the TCA6507 can either drive LEDs or act as output-only GPIOs. To make this distinction in devicetree we use the "compatible" property. If the device attached to a line is "compatible" with "gpio", we treat it like a GPIO. If it is "compatible" with "led" (or if no "compatible" value is set) we treat it like an LED. (cooloney@gmail.com: fix typo in the subject) Signed-off-by: NNeilBrown <neilb@suse.de> Signed-off-by: NBryan Wu <cooloney@gmail.com>
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- 24 1月, 2014 3 次提交
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由 Heiko Stuebner 提交于
Add binding documentation for the hym8563 rtc chip. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Grant Likely <grant.likely@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Richard Weinberger <richard.weinberger@gmail.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Alexander Shiyan 提交于
This patch allows the driver to be enabled with devicetree. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Xiubo Li 提交于
Fix the usage of simple card widgets routing property, and make it the same with simple card routing property name. Signed-off-by: NXiubo Li <Li.Xiubo@freescale.com> Signed-off-by: NMark Brown <broonie@linaro.org>
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- 23 1月, 2014 4 次提交
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由 Heiko Stübner 提交于
It seems I forgot to add the vendor prefix for rockchip to the vendor-prefix list. Therefore add it now. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Tony Prisk 提交于
The binding document for the vt8500/wm8xxx SoC UART driver is missing. This patch adds the binding document. Signed-off-by: NTony Prisk <linux@prisktech.co.nz> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Thierry Reding 提交于
The head number of a given display controller is fixed in hardware and required to program outputs appropriately. Relying on the driver probe order to determine this number will not work, since that could yield a situation where the second head was probed first and would be assigned head number 0 instead of 1. By explicitly specifying the head number in the device tree, it is no longer necessary to rely on these assumptions. As a fallback, if the property isn't available, derive the head number from the display controller node's position in the device tree. That's somewhat more reliable than the previous default but not a proper solution. Tested-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NThierry Reding <treding@nvidia.com>
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由 Daniel Tang 提交于
This patch adds support for the interrupt controllers found in some TI-Nspire models. FIQ support was taken out to simplify the driver code and may be added in later. Since Linux on this platform doesn't really use FIQs, this wasn't really that important in the first place. [ tglx: Made zevio_handle_irq static and reordered __init functions ] Signed-off-by: NDaniel Tang <dt.tangr@gmail.com> Acked-by: NGrant Likely <grant.likely@secretlab.ca> Link: http://lkml.kernel.org/r/1386223937-12189-1-git-send-email-dt.tangr@gmail.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 22 1月, 2014 1 次提交
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由 Vince Bridgers 提交于
This change adds a parameter for the Synopsys 10/100/1000 stmmac Ethernet driver to configure the maximum frame size supported by the EMAC driver. Synopsys allows the FIFO sizes to be configured when the cores are built for a particular device, but do not provide a way for the driver to read information from the device about the maximum MTU size supported as limited by the device's FIFO size. Signed-off-by: NVince Bridgers <vbridgers2013@gmail.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 21 1月, 2014 4 次提交
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由 Sachin Kamat 提交于
LDO indices start from 1. Fix the example appropriately. Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Rhyland Klein 提交于
The EC has specific timing it requires. Add support for an optional delay after raising CS to fix timing issues. This is configurable based on a DT property "google,cros-ec-spi-msg-delay". If this property isn't set, then no delay will be added. However, if set it will cause a delay equal to the value passed to it to be inserted at the end of a transaction. Signed-off-by: NRhyland Klein <rklein@nvidia.com> Reviewed-by: NBernie Thompson <bhthompson@chromium.org> Reviewed-by: NAndrew Bresticker <abrestic@chromium.org> Acked-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Milo Kim 提交于
Bindings for LP3943 MFD, GPIO and PWM controller are added. Signed-off-by: NMilo Kim <milo.kim@ti.com> Acked-by: NThierry Reding <thierry.reding@gmail.com> Signed-off-by: NLee Jones <lee.jones@linaro.org>
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由 Jason Cooper 提交于
Add some guidance documentation about what to do with device tree bindings and how ABI stability is to be handled. Signed-off-by: NJason Cooper <jason@lakedaemon.net> [grant.likely: added some clarification on subsystem binding rules] Signed-off-by: NGrant Likely <grant.likely@linaro.org>
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- 20 1月, 2014 5 次提交
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由 Jonas Jensen 提交于
The MOXA ART SoC has a DMA controller capable of offloading expensive memory operations, such as large copies. This patch adds support for the controller including four channels. Two of these are used to handle MMC copy on the UC-7112-LX hardware. The remaining two can be used in a future audio driver or client application. Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
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由 Chen-Yu Tsai 提交于
The Allwinner A20 has an ethernet controller that seems to be an early version of Synopsys DesignWare MAC 10/100/1000 Universal, which is supported by the stmmac driver. Allwinner's GMAC requires setting additional registers in the SoC's clock control unit. The exact version of the DWMAC IP that Allwinner uses is unknown, thus the exact feature set is unknown. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Chen-Yu Tsai 提交于
The snps,phy-addr device tree property is non-standard, and should be removed in favor of proper phy node support. Remove it from the binding documents and warn if the property is still used. Most PHYs respond to address 0, but a few don't, so auto-detect PHY address by default, to make up for the lack of explicit address selection. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Chen-Yu Tsai 提交于
The DWMAC has a reset assert line, which is used on some SoCs. Add an optional reset control to stmmac driver core. To support reset control deferred probing, this patch changes the driver probe function to return the actual error, instead of just -EINVAL. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Sergei Shtylyov 提交于
Though described as required, the "phy-handle" property for the DaVinci EMAC binding is actually optional, as the driver will happily function without it, assuming 100/FULL link; the property is not specified either in the example device node, or in the actual EMAC device nodes for DA850 and AM3517 device trees. Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 18 1月, 2014 9 次提交
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由 Tang Yuantian 提交于
Adds the clock bindings for Freescale PowerPC CoreNet platforms Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> [scottwood@freescale.com: fixed clock-frequency in example] Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Zhangfei Gao 提交于
Remove clk_table and directly use ios->clock as clock source rate. Abstract init clock rate and max clock limitation in clk.c Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Acked-by: NSeungwon Jeon <tgih.jun@samsung.com> Signed-off-by: NChris Ball <chris@printf.net>
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由 Lothar Waßmann 提交于
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Florian Vaussard 提交于
Using "epfl" for Ecole Polytechnique Fédérale de Lausanne. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Florian Vaussard 提交于
Using "gumstix" for Gumstix Inc. Signed-off-by: NFlorian Vaussard <florian.vaussard@epfl.ch> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Lothar Waßmann 提交于
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de> Signed-off-by: NRob Herring <robh@kernel.org>
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由 Tero Kristo 提交于
OMAP3 has interface clocks in addition to functional clocks, which require special handling for the autoidle and idle status register offsets mainly. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 J Keerthy 提交于
The patch adds support for DRA7 PCIe APLL. The APLL sources the optional functional clocks for PCIe module. APLL stands for Analog PLL. This is different when comapred with DPLL meaning Digital PLL, the phase detection is done using an analog circuit. Signed-off-by: NJ Keerthy <j-keerthy@ti.com> Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tero Kristo 提交于
ti,mux-clock provides now a binding for basic mux support. This is just using the basic clock type. Signed-off-by: NTero Kristo <t-kristo@ti.com> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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