- 05 2月, 2010 32 次提交
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由 Miguel Aguilar 提交于
This patch adds the generic Voice Codec support for the DM365 based platforms. Signed-off-by: NMiguel Aguilar <miguel.aguilar@ridgerun.com> Acked-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
When supporting I2C/SPI based on-board PLLs like CDCE949, it is essential that clk->set_rate be able to sleep. Currently, this is not possible because clk->set_rate is called from within spin-lock in clk_set_rate This patch brings clk->set_rate outside of the spin-lock and lets the individual set_rate implementations achieve serialization through appropiate means. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Philby John 提交于
Patch adds SDA and SCL pin numbers to the i2c platform data structure for Davinci DM355 and DM6446. This at present is used for i2c bus recovery. TODO: Add SDA and SCL pin number information to include all Davinci platforms such as dm355-leopard, dm365, dm646x, da8xx etc. Signed-off-by: NPhilby John <pjohn@in.mvista.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
Currently da850/omap-l138 supports only one channel controller instance of EDMA though EDMA driver as such supports multiple channel controller instances. This patch adds platform data for the 2nd EDMA channel controller. As, the platform data differ between da830/omap-l137 and da850/omap-l138, existing code has been re-shuffled to accommodate this. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
Currently, the edma_noevent list is passed from platform data. But on some architectures, there will be many EDMA channels which will not be used at all. This patch scans all the platform devices and then builds a list of events which are not being used. The unused event list will be used to allocate EDMA channels in case of EDMA_CHANNEL_ANY usage instead of the edma_noevent being used earlier for this purpose. This patch is based on David Brownells's suggestion at http://article.gmane.org/gmane.linux.davinci/15176. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
Though edma_alloc_channel api was looping through the available channel controllers in EDMA_CHANNEL_ANY case, it was never returning the channel for 2nd channel controller, if 1st channel controller had no free channels. This issue has been fixed with this patch. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
Some architectures have only one channel controller, but the edma_alloc_channel api loops twice to findout the free channel available in EDMA_CHANNEL_ANY case. A new variable has been introduced to keep count of number of channel controllers being used on a particular architecture. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
Currently, edma_alloc_channel api is returning the channel number without prepending the controller on which the channel was allocated. So, if a channel is allocated on 2nd controller, calls subsequent to edma_alloc_channel would never know that channel was allocated on the 2nd controller, and continue to operate on 1st controller, resulting in edma failure. This patch fixes this issue. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Nageswari Srinivasan 提交于
This patch adds the CDCE949 reference oscillator to the davinci clock list. On the DM6467T EVM, the CDCE949 is responsible for generating the pixel clock for display. On the DM6467 EVM, this pixel clock was being obtained from an internal source. This is not possible on the DM6467T EVM because of the presence of a 33MHz oscillator. The TSIF module also requires the CDCE949 to generate the data clocks. The actual clock definitions will be added by patches adding support for DM6467T VPIF and TSIF. This patch mearly lays the foundation for that work. Signed-off-by: NNageswari Srinivasan <nageswari@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Nageswari Srinivasan 提交于
This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by: NNageswari Srinivasan <nageswari@ti.com> Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
This patch adds support for registering for suspend-to-RAM functionality on da850/omap-l138 SoCs. da850 supports wakeup based on external event and RTC alarm. Currently only RTC alarm based wakeup is supported. Support for wakeup based on external event will be added as later improvements. For scheduling an alarm event on RTC some useful code is present in Documentation/rtc.txt Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sandeep Paulraj 提交于
In DM365 Q0, Q1 and Q2 are used by codecs. LSP drivers should use Q3. This patch changes the default queue for DM365. Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Chaithrika U S 提交于
Some modules do not have PSC to control their clocks. The 'lpsc' field in the clk structure is 0 for such clocks. In the clock disable function check for CLK PSC flag before disabling the PSC. If this is not taken care of then it may so happen that module controlled by LPSC 0 is erroneously disabled. Signed-off-by: NChaithrika U S <chaithrika@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sriramakrishnan 提交于
The davinci EMAC peripheral is also available on other TI platforms -notably TI AM3517 SoC. This patch modifies the config option and the platform structure header files so that the driver can be reused on non-davinci platforms as well. Signed-off-by: NSriramakrishnan <srk@ti.com> Acked-by: NChaithrika U S <chaithrika@ti.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
This patch initializes the platform data to enable 4-bit ecc support on DA850/OMAP-L138. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sudhakar Rajashekhara 提交于
On DA850/OMAP-L138, NOR flash partition was starting from offset ZERO erasing the UBL and u-boot when the complete NOR is erased. This patch moves the start of the partition to 512K, after the bootloaders and u-boot env variables. This patch also creates a new partition on NOR Flash to store Linux kernel image. Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Move /proc/davinci_clocks to /sys/kernel/debug/davinci_clocks (debugfs). debugfs is more suited for this since the clock dump is debug information. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
This patch modifies clock dump to take care of clock tress rooted at multiple oscillators. Current code assumes the entire tree is rooted on a single oscillator. When using off-chip clock synthesizers, some of the clocks can be obtained from a different on-board oscillator. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
DM6467T (T for Turbo) is a newer and faster DM6467 part from TI. The new part supports 1080p video and has the ARM running at 495MHz. More SoC information: http://focus.ti.com/docs/prod/folders/print/tms320dm6467t.html Spectrum Digital, Inc has a new EVM for this part. It is _mostly_ same as the older DM6467 EVM except for a 33MHz crystal input and THS8200 video encoder for 1080p support. The meat of this patch is dedicated to initializing the crystal frequency from EVM board file. Additional notes: I did consider some alternative ways to make the crystal input board specific including - (1) having board code initialize the crystal frequency using the first member of soc_info->cpu_clks array (2) introducing a new ref_clk_rate member in soc_info structure. But, the current way seems to be the simplest and least intruding considering that both the clock array and SoC info structure are actually private to the SoC file. Also the fact that davinci_common_init() initializes both the soc_info and clocks in one go. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Currently all the #defines and static variables in the board-dm646x-evm.c file are located right at the start of the file because of which the related code is not together - making reading the code difficult. This patch moves around the code keeping related code together. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Leave a comment explaining the constant value of 27Mhz used in include/mach/timex.h for all DaVinci platforms. Many of the platforms actually run at 24MHz timer frequency (Eg. EVMs of DM355, DM365 and OMAP-L1). The comment also serves as a porting alert. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Create static map for internal SRAM and populate SRAM base and size in soc_info structure to allow SRAM allocation functions from arch/arm/mach-davinci/sram.c to work. On DA850 SRAM is used for suspend-to-RAM implementation in places where DDR2 cannot be accessed as its clocks are stopped. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
On omap-l1 devices the PLL registers can be locked from writes. Currently the cpufreq rate setting code unlocks PLL0 before the write actually happens. With suspend support getting added PLL1 registers need be be unlocked as well. To facilitate this, unlock both PLLs during the init time itself. This also obviates the need to unlock PLL registers for each CPUFreq transtition. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
When suspend is supported, both cpuidle and suspend code need to work on DDR2 registers. Instead of mapping the DDR2 registers twice, do it once outside of cpuidle driver and let cpuidle driver get the virtual base address of DDR2 registers. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
psc.h contains register defines for PSC module which need to be accessed in assembly code which helps the DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock using PSC is a part of the sleep procedure. Also, the PLL related hardware definitions in clock.h are needed in assembly code to bypass the DDR2 PLL. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
The motivation behind the change is to use the same definitions in the assembly code responsible for suspending the SoC, a part of which is to clock gate the DDR2 clock. Note that the assembly code cannot invoke the C function meant for this. The main reason being that stack in DDR2 cannot be accessed while DDR2 clock is being clock gated. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
Move defintions of DDR2 controller registers to memory.h from cpuidle.c. The motivation behind the change is to be able to use these defintions in assembly code that puts DDR2 in self-refresh and enables the SoC to enter suspend state. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Sekhar Nori 提交于
OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by: NSekhar Nori <nsekhar@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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由 Murali Karicheri 提交于
This patch adds following changes:- 1) add sub device configuration data for TVP5146 used by vpfe capture 2) registers platform devices for vpfe_capture, isif and vpss 3) defines hardware resources for the devices listed under 2) 4) defines clock aliase for isif driver 5) adding setup_pinmux() for isif Signed-off-by: NMurali Karicheri <m-karicheri2@ti.com> Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
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- 30 1月, 2010 3 次提交
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由 David Miller 提交于
Here are the sparc bits to remove TIF_ABI_PENDING now that set_personality() is called at the appropriate place in exec. Signed-off-by: NDavid S. Miller <davem@davemloft.net> Cc: stable@kernel.org Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 H. Peter Anvin 提交于
Now that the previous commit made it possible to do the personality setting at the point of no return, we do just that for ELF binaries. And suddenly all the reasons for that insane TIF_ABI_PENDING bit go away, and we can just make SET_PERSONALITY() just do the obvious thing for a 32-bit compat process. Everything becomes much more straightforward this way. Signed-off-by: NH. Peter Anvin <hpa@zytor.com> Cc: stable@kernel.org Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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由 Linus Torvalds 提交于
'flush_old_exec()' is the point of no return when doing an execve(), and it is pretty badly misnamed. It doesn't just flush the old executable environment, it also starts up the new one. Which is very inconvenient for things like setting up the new personality, because we want the new personality to affect the starting of the new environment, but at the same time we do _not_ want the new personality to take effect if flushing the old one fails. As a result, the x86-64 '32-bit' personality is actually done using this insane "I'm going to change the ABI, but I haven't done it yet" bit (TIF_ABI_PENDING), with SET_PERSONALITY() not actually setting the personality, but just the "pending" bit, so that "flush_thread()" can do the actual personality magic. This patch in no way changes any of that insanity, but it does split the 'flush_old_exec()' function up into a preparatory part that can fail (still called flush_old_exec()), and a new part that will actually set up the new exec environment (setup_new_exec()). All callers are changed to trivially comply with the new world order. Signed-off-by: NH. Peter Anvin <hpa@zytor.com> Cc: stable@kernel.org Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 29 1月, 2010 2 次提交
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由 Russell King 提交于
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Jeff Garrett 提交于
Turned out to cause trouble on single IOH machines, and is superceded by _CRS on multi-IOH machines with production BIOSes. Signed-off-by: NJeff Garrett <jeff@jgarrett.org> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 28 1月, 2010 3 次提交
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由 David VomLehn 提交于
The MIPS processor is limited to 64 external interrupt sources. Using a greater number without IRQ sharing requires reading platform-specific registers. On such platforms, reading the IntCtl register to determine which interrupt corresponds to a timer interrupt will not work. On MIPSR2 systems there is a solution - the TI bit in the Cause register, specifically indicates that a timer interrupt has occured. This patch uses that bit to detect interrupts for MIPSR2 processors, which may be expected to work regardless of how the timer interrupt may be routed in the hardware. Signed-off-by: David VomLehn (dvomlehn@cisco.com) To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/804/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 David VomLehn 提交于
Pre-compute addresses for the basic ASIC registers. This speeds up access and allows memory for unused configurations to be freed. In addition, uninitialized register addresses will be returned as NULL to catch bad usage quickly. Signed-off-by: NDavid VomLehn <dvomlehn@cisco.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/806/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Alexander Clouter 提交于
POSIX requires $((<expression>)) arithmetic in sh only to have long arithmetic so on 32-bit sh binaries might do only 32-bit arithmetic but the arithmetic done in arch/mips/boot/compressed/Makefile needs 64-bit. I play with the AR7 platform, so VMLINUX_LOAD_ADDRESS is 0xffffffff94100000, and for an example 4MiB kernel VMLINUZ_LOAD_ADDRESS is made out to be: ---- alex@berk:~$ bash -c 'printf "%x\n" $((0xffffffff94100000 + 0x400000))' ffffffff94500000 alex@berk:~$ dash -c 'printf "%x\n" $((0xffffffff94100000 + 0x400000))' 80000000003fffff ---- The former is obviously correct whilst the later breaks things royally. Fortunately working with only the lower 32bit's works for both bash and dash: ---- $ bash -c 'printf "%x\n" $((0x94100000 + 0x400000))' 94500000 $ dash -c 'printf "%x\n" $((0x94100000 + 0x400000))' 94500000 ---- So, we can split the original 64bit string to two parts, and only calculate the low 32bit part, which is big enough (1GiB kernel sizes anyone?) for a normal Linux kernel image file, now, we calculate the VMLINUZ_LOAD_ADDRESS like this: 1. if present, append top 32bit of VMLINUX_LOAD_ADDRESS" as a prefix 2. get the sum of the low 32bit of VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE This patch fixes vmlinuz kernel builds on systems where only a 32bit-only math shell is available. Patch Changelog: Version 2 - simplified method by using 'expr' for 'substr' and making it work with dash once again Version 1 - Revert the removals of '-n "$(VMLINUX_SIZE)"' to avoid the error of "make clean" - Consider more cases of the VMLINUX_LOAD_ADDRESS Version 0 - initial release Signed-off-by: NAlexander Clouter <alex@digriz.org.uk> Acked-by: NWu Zhangjin <wuzhangjin@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/861/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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