1. 10 12月, 2014 2 次提交
  2. 23 11月, 2014 4 次提交
  3. 11 11月, 2014 3 次提交
  4. 10 10月, 2014 1 次提交
  5. 23 12月, 2013 1 次提交
  6. 04 12月, 2013 1 次提交
  7. 14 3月, 2013 1 次提交
  8. 08 12月, 2012 1 次提交
  9. 04 12月, 2012 1 次提交
  10. 11 8月, 2011 1 次提交
  11. 24 6月, 2011 1 次提交
  12. 15 2月, 2011 1 次提交
  13. 11 1月, 2011 1 次提交
    • C
      cxgb4vf: fix mailbox data/control coherency domain race · 80ce3f67
      Casey Leedom 提交于
      For the VFs, the Mailbox Data "registers" are actually backed by
      T4's "MA" interface rather than PL Registers (as is the case for
      the PFs).  Because these are in different coherency domains, the
      write to the VF's PL-register-backed Mailbox Control can race in
      front of the writes to the MA-backed VF Mailbox Data "registers".
      So we need to do a read-back on at least one byte of the VF Mailbox
      Data registers before doing the write to the VF Mailbox Control
      register.
      Signed-off-by: NCasey Leedom <leedom@chelsio.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      80ce3f67
  14. 21 12月, 2010 1 次提交
  15. 29 11月, 2010 1 次提交
  16. 16 11月, 2010 1 次提交
  17. 13 11月, 2010 1 次提交
  18. 21 7月, 2010 1 次提交
  19. 29 6月, 2010 1 次提交