- 13 1月, 2009 1 次提交
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由 Mike Travis 提交于
Impact: cleanup, update to new cpumask API Irq_desc.affinity and irq_desc.pending_mask are now cpumask_var_t's so access to them should be using the new cpumask API. Signed-off-by: NMike Travis <travis@sgi.com>
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- 07 1月, 2009 2 次提交
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由 Yi Li 提交于
[Mike Frysinger <vapier.adi@gmail.com>: - handle bf531/bf532/bf534/bf536 variants in ipipe.h - cleanup IPIPE logic for bfin_set_irq_handler() - cleanup ipipe asm code a bit and add missing ENDPROC() - simplify IPIPE code in trap_c - unify some of the IPIPE code and fix style - simplify DO_IRQ_L1 handling with ipipe code - revert IRQ_SW_INT# addition from ipipe merge - remove duplicate get_{c,s}clk() prototypes ] Signed-off-by: NYi Li <yi.li@analog.com> Signed-off-by: NMike Frysinger <vapier.adi@gmail.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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由 Robin Getz 提交于
Signed-off-by: NRobin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 18 11月, 2008 2 次提交
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <vapier.adi@gmail.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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由 Graf Yang 提交于
Blackfin dual core BF561 processor can support SMP like features. https://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:smp-like In this patch, we provide SMP extend to Blackfin kernel and memory management code Singed-off-by: NGraf Yang <graf.yang@analog.com> Signed-off-by: NMike Frysinger <vapier.adi@gmail.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 25 6月, 2008 1 次提交
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由 Sonic Zhang 提交于
Initialize the lock of bad_irq_desc properly. The content of irq_desc array is replaced by bad_irq_desc in blackfin arch irqchip init code. So, do it properly as common irq init code. Signed-off-by: NSonic Zhang <sonic.zhang@analog.com> Signed-off-by: NBryan Wu <cooloney@kernel.org>
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- 05 8月, 2007 1 次提交
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由 Mike Frysinger 提交于
- allow people to select the feature that is unavailable to the kernel: NMI, JTAG, or CYCLES. - change default NMI handler to simply dump hardware trace buffer. - remove default NMI handler completely as calling into kernel code is not safe move example handler to wiki so people dont haphazardly copy and paste this stuff thinking its safe Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 25 7月, 2007 1 次提交
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由 Robin Getz 提交于
Add ability to expend the hardware trace buffer via a configurable software buffer - so you can have lots of history when a crash occurs. The interesting way we do printk in the traps.c confusese the checking script Signed-off-by: NRobin Getz <robin.getz@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 12 7月, 2007 1 次提交
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由 Mike Frysinger 提交于
Signed-off-by: NMike Frysinger <michael.frysinger@analog.com> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 11 6月, 2007 1 次提交
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由 Simon Arlott 提交于
Signed-off-by: NSimon Arlott <simon@fire.lp0.eu> Signed-off-by: NBryan Wu <bryan.wu@analog.com>
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- 08 5月, 2007 1 次提交
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由 Bryan Wu 提交于
This adds support for the Analog Devices Blackfin processor architecture, and currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561 (Dual Core) devices, with a variety of development platforms including those avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP, BF561-EZKIT), and Bluetechnix! Tinyboards. The Blackfin architecture was jointly developed by Intel and Analog Devices Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in December of 2000. Since then ADI has put this core into its Blackfin processor family of devices. The Blackfin core has the advantages of a clean, orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC (Multiply/Accumulate), state-of-the-art signal processing engine and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture. The Blackfin architecture, including the instruction set, is described by the ADSP-BF53x/BF56x Blackfin Processor Programming Reference http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf The Blackfin processor is already supported by major releases of gcc, and there are binary and source rpms/tarballs for many architectures at: http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete documentation, including "getting started" guides available at: http://docs.blackfin.uclinux.org/ which provides links to the sources and patches you will need in order to set up a cross-compiling environment for bfin-linux-uclibc This patch, as well as the other patches (toolchain, distribution, uClibc) are actively supported by Analog Devices Inc, at: http://blackfin.uclinux.org/ We have tested this on LTP, and our test plan (including pass/fails) can be found at: http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel [m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files] Signed-off-by: NBryan Wu <bryan.wu@analog.com> Signed-off-by: NMariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: NAubrey Li <aubrey.li@analog.com> Signed-off-by: NJie Zhang <jie.zhang@analog.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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