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  1. 08 1月, 2016 3 次提交
  3. 07 1月, 2016 2 次提交
  5. 05 1月, 2016 1 次提交
    • A
      fsl/fman: allow modular build · 46678612
      由 Arnd Bergmann 提交于 
      ARM allmodconfig fails because of the addition of the FMAN driver:

drivers/built-in.o: In function `dtsec_restart_autoneg':
binder.c:(.text+0x173328): undefined reference to `mdiobus_read'
binder.c:(.text+0x173348): undefined reference to `mdiobus_write'
drivers/built-in.o: In function `dtsec_config':
binder.c:(.text+0x173d24): undefined reference to `of_phy_find_device'
drivers/built-in.o: In function `init_phy':
binder.c:(.text+0x1763b0): undefined reference to `of_phy_connect'
drivers/built-in.o: In function `stop':
binder.c:(.text+0x176014): undefined reference to `phy_stop'
drivers/built-in.o: In function `start':
binder.c:(.text+0x176078): undefined reference to `phy_start'

The reason is that the driver uses PHYLIB, but that is a loadable
module here, and fman itself is built-in.

This patch makes it possible to configure fman as a module as well
so we don't change the status of PHYLIB in an allmodconfig kernel,
and it adds a 'select PHYLIB' statement to ensure that phylib is
always built-in when fman is.

The driver uses "builtin_platform_driver(fman_driver);", which means
it cannot be unloaded, but it's still possible to have it as a loadable
module that gets loaded once and never removed.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: 5adae51a ("fsl/fman: Add FMan MURAM support")
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      46678612
  7. 28 12月, 2015 6 次提交
  9. 17 12月, 2015 2 次提交
  11. 09 12月, 2015 1 次提交
    • A
      net: fsl: avoid 64-bit warning on pq_mdio · 8cde3e44
      由 Arnd Bergmann 提交于 
      The pq_mdio driver can now be built for ARM64, where we get a format
string warning:

drivers/net/ethernet/freescale/fsl_pq_mdio.c: In function 'fsl_pq_mdio_probe':
drivers/net/ethernet/freescale/fsl_pq_mdio.c:467:25: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long int' [-Wformat=]

The argument is an implicit ptrdiff_t from the subtraction of two pointers,
so we should use the %z format string modifier to make this work on 64-bit
architectures.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Fixes: fe761bcb ("net: fsl: expands dependencies of NET_VENDOR_FREESCALE")
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      8cde3e44
  13. 04 12月, 2015 1 次提交
  15. 01 12月, 2015 2 次提交
  17. 25 11月, 2015 1 次提交
  19. 24 11月, 2015 1 次提交
  21. 23 11月, 2015 1 次提交
  23. 19 11月, 2015 1 次提交
  25. 02 11月, 2015 1 次提交
  27. 28 10月, 2015 1 次提交
  29. 26 10月, 2015 3 次提交
  31. 16 10月, 2015 1 次提交
  33. 13 10月, 2015 2 次提交
    • G
      net/fsl_pq_mdio: fix computed address for the TBI register · 3bb35ac4
      由 Gerlando Falauto 提交于 
      commit afae5ad7
  "net/fsl_pq_mdio: streamline probing of MDIO nodes"

added support for different types of MDIO devices:
1) Gianfar MDIO nodes that only map the MII registers
2) Gianfar MDIO nodes that map the full MDIO register set
3) eTSEC2 MDIO nodes (which map the full MDIO register set)
4) QE MDIO nodes (which map only the MII registers)

However, the implementation for types 1 and 4 would mistakenly assume
a mapping of the full MDIO register set, thereby computing the address
for the TBI register starting from the containing structure.
The TBI register would therefore be accessed at a wrong (much bigger)
address, not giving the expected result at all.
This patch restores the correct behavior we had prior to the above one.

The consequences of this bug are apparent when trying to access a PHY
with the same address as the value contained in the initial value of
the TBI register (normally 0); in that case you'll get answers from the
internal TBI device (even though MDIO/MDC pins are actually *also*
toggling on the physical bus!).
Beware that you also need to add a fake tbi node to your device tree
with an unused address.

Notice how this fix is related to commit
22066949
  "powerpc: Add TBI PHY node to first MDIO bus"

which fixed the behavior in kernel 3.3, which was later broken by the
above commit on kernel 3.7.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
Cc: Timur Tabi <timur@tabi.org>
Cc: David S. Miller <davem@davemloft.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3bb35ac4
    • G
      net/fsl_pq_mdio: check TBI address for consistency with mapped range · 3dd03e52
      由 Gerlando Falauto 提交于 
      When configuring the MDIO subsystem it is also necessary to configure
the TBI register. Make sure the TBI is contained within the mapped
register range in order to:
a) make sure the address is computed correctly
b) make users aware that we're actually accessing that register

In case of error, print a message but continue anyway.
Signed-off-by: NGerlando Falauto <gerlando.falauto@keymile.com>
Cc: Timur Tabi <timur@tabi.org>
Cc: David S. Miller <davem@davemloft.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3dd03e52
  35. 07 10月, 2015 1 次提交
    • C
      gianfar: Add WAKE_UCAST and "wake-on-filer" support · 3e905b80
      由 Claudiu Manoil 提交于 
      This enables eTSEC's filer (Rx parser) and the FGPI Rx
interrupt (Filer General Purpose Interrupt) as a wakeup
source event.

Upon entering suspend state, the eTSEC filer is given
a rule to match incoming L2 unicast packets.  A packet
matching the rule will be enqueued in the Rx ring and
a FGPI Rx interrupt will be asserted by the filer to
wakeup the system.  Other packet types will be dropped.
On resume the filer table is restored to the content
before entering suspend state.
The set of rules from gfar_filer_config_wol() could be
extended to implement other WoL capabilities as well.

The "fsl,wake-on-filer" DT binding enables this capability
on certain platforms that feature the necessary power
management infrastructure, targeting mainly printing and
imaging applications.
(refer to Power Management section of the SoC Ref Man)

Cc: Li Yang <leoli@freescale.com>
Cc: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: NClaudiu Manoil <claudiu.manoil@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3e905b80
  37. 05 10月, 2015 1 次提交
    • A
      net: fec: avoid timespec use · be7ccdc3
      由 Arnd Bergmann 提交于 
      The fec_ptp_enable_pps uses an open-coded implementation of ns_to_timespec,
which will be removed eventually as it is not y2038-safe on 32-bit
architectures. Two more instances of the same code in this file were
already converted to use the safe ns_to_timespec64 in commit 6630514f
("ptp: fec: use helpers for converting ns to timespec"), this changes
the last one as well.

The seconds portion here is actually unused and we could just remove the
timespec variable, but using ns_to_timespec64 can still be better as the
implementation can be hand-optimized in the future.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Richard Cochran <richardcochran@gmail.com>
Cc: Fugang Duan <b38611@freescale.com>
Cc: Luwei Zhou <b45643@freescale.com>
Cc: Frank Li <Frank.Li@freescale.com>
Acked-by: NRichard Cochran <richardcochran@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      be7ccdc3
  39. 29 9月, 2015 1 次提交
  41. 25 9月, 2015 3 次提交
  43. 22 9月, 2015 1 次提交
  45. 10 9月, 2015 1 次提交
    • N
      net: fec: add netif status check before set mac address · 9638d19e
      由 Nimrod Andy 提交于 
      There exist one issue by below case that case system hang:
ifconfig eth0 down
ifconfig eth0 hw ether 00:10:19:19:81:19

After eth0 down, all fec clocks are gated off. In the .fec_set_mac_address()
function, it will set new MAC address to registers, which causes system hang.

So it needs to add netif status check to avoid registers access when clocks are
gated off. Until eth0 up the new MAC address are wrote into related registers.

V2:
As Lucas Stach's suggestion, add a comment in the code to explain why it needed.

CC: Lucas Stach <l.stach@pengutronix.de>
CC: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NFugang Duan <B38611@freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      9638d19e
  47. 06 9月, 2015 1 次提交
  49. 03 9月, 2015 1 次提交