Now using group_desc structure instead of imx_pin_group.

Also leveraging generic functions to retrieve groups count/name/pins.

The imx_free_pingroups function can be removed since it is now handled by
the core driver during unregister.

Finally the device tree parsing is moved after the pinctrl driver registration
since this latter initializes the radix trees.
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

These four pins are for SDC4, not SDC1. They are grouped for
SDC4 later in the file so this must be a typo.
Reviewed-by: NBjörn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We can now drop the driver specific code for managing functions.
Signed-off-by: NTony Lindgren <tony@atomide.com>
[Replaces GENERIC_PINMUX with GENERIC_PINMUX_FUNCTIONS]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We can now drop the driver specific code for managing groups.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We can add generic helpers for function handling for cases where the pin
controller driver does not need to use static arrays.
Signed-off-by: NTony Lindgren <tony@atomide.com>
[Renamed the Kconfig item and moved things around]
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rename the symbol PINCTRL_GENERIC to PINCTRL_GENERIC_GROUPS since
it all pertains to groups. Replace everywhere.

ifdef out the radix tree and the struct when not using the
generic groups.

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We can add generic helpers for pin group handling for cases where the pin
controller driver does not need to use static arrays.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

It confused me a bit so it may confuse others. Make it crystal
clear what is going on here for any future readers.

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Having the pin control framework call pin controller functions
before it's probe has finished is not nice as the pin controller
device driver does not yet have struct pinctrl_dev handle.

Let's fix this issue by adding deferred work for late init. This is
needed to be able to add pinctrl generic helper functions that expect
to know struct pinctrl_dev handle. Note that we now need to call
create_pinctrl() directly as we don't want to add the pin controller
to the list of controllers until the hogs are claimed. We also need
to pass the pinctrl_dev to the device tree parser functions as they
otherwise won't find the right controller at this point.
Signed-off-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This change is inspired from the pinctrl-single architecture.

The problem with current implementation is that it isn't possible
to add/remove functions and/or groups dynamically. The radix tree
offers an easy way to do so. The intent is to offer a follow-up
patch later that will enable the use of pinctrl nodes in dt-overlays.
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Otherwise can't dynamically update fields such as ngroups which can
change over time (with a dt-overlay for instance).
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Trivial fixe to spelling mistake "Ivalid" to "Invalid" in
dev_err  error message.
Signed-off-by: NColin Ian King <colin.king@canonical.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This is a non-functional change, which deletes code duplication in two
of four if-if branches by reordering the checks. Functional identity
of the code change can be shown by running through the whole truth table
of boolean arguments.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch updates my email address as I no longer have access to the old
one.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add some tab in order to improve indentation.
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Reference to 'sys2pci_np' should be dropped in all cases here, not only in
error handling path.
Signed-off-by: NChristophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This activates strict mode muxing for the STM32 pin controllers,
as these do not allow GPIO and functions to use the same pin
simultaneously.
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: NPatrice Chotard <patrice.chotard@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds support for new Bank and adds IRQCHIP_SKIP_SET_WAKE flag.
Reviewed-by: NS-k, Shyam-sundar <Shyam-sundar.S-k@amd.com>
Signed-off-by: NNehal Shah <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The patch introducing the g5 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms and the AST2500 evaluation board.
Now, update the bindings document to reflect the complete functionality
and implement the necessary pin configuration tables in the driver.
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The patch introducing the g4 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms. Now, update the bindings document
to reflect the complete functionality and implement the necessary pin
configuration tables in the driver.

Cc: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Acked-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The System Control Unit IP block in the Aspeed SoCs is typically where
the pinmux configuration is found, but not always. A number of pins
depend on state in one of LPC Host Control (LHC) or SoC Display
Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
means to adjust these as necessary.

We use syscon to cast a regmap over the GFX and LPC blocks, which is
used as an arbitration layer between the relevant driver and the pinctrl
subsystem. The regmaps are then exposed to the SoC-specific pinctrl
drivers by phandles in the devicetree, and are selected during a mux
request by querying a new 'ip' member in struct aspeed_sig_desc.
Signed-off-by: NAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: NJoel Stanley <joel@jms.id.au>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use the new gpiochip_irqchip_add_nested() and
gpiochip_set_nested_irqchip() calls to properly created
a nested irqchip and mark all child irqs properly with
their parent IRQ.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This fixes a problem where sx150x_regmap_reg_width() returns 8 for the
data register (reg 0) for sx1504 where it should return 4, and return
a correct 8 for sx1505 but for the wrong reason (both chips lack the
'advanced' register). This is not a real problem, since nothing depends
on the function returning 4 or 8, and certainly not if it is returning
8 for the wrong reason. But fix this to avoid nasty surprises down the
line.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This matches the datasheets and is less confusing since the register
has nothing to with advancing anything.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The code assumes 8-bit or 16-bit width registers, but three of the
chips (sx1501/sx1504/sx1507) are 4-bit. So, try to handle 4-bit chips as
well, they leave the high part of each register unused.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

the default mode of GPIO16 pin is gpio, when set EINT16 to
IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be
fixed when set its default mode as usb iddig.
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

It should be possible to use the GPIOLIB_IRQCHIP helper
library with the BCM2835 driver since it is a pretty straight
forward cascaded irqchip.

The only difference from other drivers is that the BCM2835
has several banks for a single gpiochip, and each bank has
a separate IRQ line. Instead of creating one gpiochip per
bank, a single gpiochip covers all banks GPIO lines. This
makes it necessary to resolve the bank ID in the IRQ
handler.

The GPIOLIB_IRQCHIP allows several IRQs to be cascaded off
the same gpiochip by calling gpiochip_set_chained_irqchip()
repeatedly, but we have been a bit short on examples
for how this should be handled in practice, so this is intended
as an example of how this can be achieved.

The old code did not model the chip as a chained interrupt
handler, but this patch also rectifies that situation.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: NStefan Wahren <stefan.wahren@i2se.com>
Tested-by: NEric Anholt <eric@anholt.net>
Acked-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds a new driver for pinconf on TI DA850/OMAP-L138/AM18XX. These
SoCs have a separate controller for controlling pullup/pulldown groups.
Signed-off-by: NDavid Lechner <david@lechnology.com>
Reviewed-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

We switch the default handler to be handle_bad_irq() instead of
handle_simple_irq() (which was not correct anyway).
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Untested, register offsets carefully copied from datasheets.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

All other registers on these chips are 8-bit, but reg_sense is 16-bits
and therefore needs to be moved down one notch.
This was apparently overlooked in the conversion to regmap, which only
updated the register locations for the 16-bit chips.

Fixes: 6489677f ("pinctrl-sx150x: Replace sx150x_*_cfg by means of regmap API")
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fixes: 6e408ed8 ("pinctrl: imx: fix initialization of imx_pinctrl_desc")
Reviewed-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Signed-off-by: NGary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If the chip does not have an oscio pin, all pins are configured in
the same regmap register making it trivial to update all pins at
once, so do that. If an oscio pin is present, there needs to be
more locking in place to handle all cases correctly, so this is
skipped.
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NPeter Rosin <peda@axentia.se>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use builtin_platform_driver() helper to simplify the code.
Signed-off-by: NGeliang Tang <geliangtang@gmail.com>
Acked-by: NHongzhou Yang <hongzhou.yang@mediatek.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Use builtin_platform_driver() helper to simplify the code.
Signed-off-by: NGeliang Tang <geliangtang@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Smatch complains that we dereference "map" before testing it for NULL
which is true.  We should be testing "*map" instead.  Also on the error
path, we should free *map and set it to NULL.
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When debugging it helps to see exactly which pin goes where,
so make it very detailed.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>