- 18 7月, 2014 4 次提交
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由 Anssi Hannula 提交于
The S/PDIF rxtx4 and rxtx6 clock inputs are "ESAI_HCKT" and "MLB clock", respectively, according to the SoC documentation, and they are currently mapped to clocks "esai" and "mlb". However, they do not seem to actually work correctly. Testing on a Cubox-i system with fsl_spdif driver forced to select one of those as input will result in I/O errors on audio playback, which I believe means missing clock signal. Possibly the "ESAI_HCKT" and "MLB clock" refer to some other clocks related to ESAI and MLB, or we are missing something else. Since audio playback will not work if fsl_spdif selects these clocks (which happens rarely), set the inputs do dummy clocks, at least for now. Signed-off-by: NAnssi Hannula <anssi.hannula@iki.fi> Cc: Mark Brown <broonie@kernel.org> Acked-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Anssi Hannula 提交于
The rxtx2 clock of i.MX6 S/PDIF is currently set to "asrc" clock. However, according to SoC documentation, rxtx2 is connected to ASRC_EXT_CLK, a different external clock. Testing on Cubox-i system seems to confirm that: when fsl_spdif is forced to select rxtx2 as input clock, audio playback fails with an I/O error. Set rxtx2 to the dummy clock by default to prevent fsl_spdif from selecting it. Signed-off-by: NAnssi Hannula <anssi.hannula@iki.fi> Cc: Mark Brown <broonie@kernel.org> Acked-by: NNicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Lothar Waßmann 提交于
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Philipp Zabel 提交于
This patch adds CSI subnodes for IPU1 and IPU2 that will contain ports and endpoints connecting to external elements in the video pipeline. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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- 16 5月, 2014 1 次提交
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由 Lucas Stach 提交于
The new bindings drops one clock, renames the others and drops the old interrupt mapping. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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- 30 4月, 2014 1 次提交
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由 Marek Vasut 提交于
Add alias for FEC ethernet on i.MX to allow bootloaders (like U-Boot) patch-in the MAC address for FEC using this alias. Signed-off-by: NMarek Vasut <marex@denx.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 14 4月, 2014 3 次提交
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由 Shawn Guo 提交于
Per bindings of fixed-clock, #clock-cells is a required property. Let's add it for those fixed rate clocks. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Lucas Stach 提交于
Those two properties should have been set to zero, which is the same as not specifying them. Having address-cells set to 1 causes OF interrupt mapping routines to add 1 to the interrupt-cells property and as result fail because all calculations are off by one. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Lucas Stach 提交于
As defined by the common PCI bindings. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Acked-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 08 3月, 2014 1 次提交
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由 Philipp Zabel 提交于
This patch connects IPU and display encoder (HDMI, LVDS, MIPI) device tree nodes, as well as parallel displays on the DISP0 and DISP1 outputs, using the OF graph bindings described in Documentation/devicetree/bindings/media/video-interfaces.txt The IPU ports correspond to the two display interfaces. The order of endpoints in the ports is arbitrary. Each encoder with an associated input multiplexer has multiple input ports in the device tree. The order and reg property of the ports must correspond to the multiplexer input order. Since the imx-drm node now only needs to contain links to the display interfaces, it can be moved to the SoC dtsi level. At the board level, only connections between the display interface ports and encoders or panels have to be added. Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 24 2月, 2014 2 次提交
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由 Russell King 提交于
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de> Acked-by: NShawn Guo <shawn.guo@linaro.org> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Extracted from another patch by Fabio Estevam, this adds the DT configuration for HDMI output on the IMX6 SoCs Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de> Acked-by: NShawn Guo <shawn.guo@linaro.org> Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 10 2月, 2014 5 次提交
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由 Markus Pargmann 提交于
imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online reconfiguration and needs this for correct interaction with SDMA. This patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs. Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Sascha Hauer 提交于
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Frank Li 提交于
Enable dma support for espci controller Signed-off-by: NFrank Li <Frank.Li@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Peter Chen 提交于
We need to use controller id to access different register regions for mxs phy. Signed-off-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Peter Chen 提交于
Add anatop phandle for usbphy Signed-off-by: NPeter Chen <peter.chen@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 09 2月, 2014 8 次提交
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由 Troy Kisky 提交于
We need to be able to override interrupts in board file to workaround a hardware bug for ethernet interrupts waking the processor by using interrupts-extended. So, use interrupts-extended here as well. Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
Instead of calling the regulator for the ARM core as 'cpu', let's rename it as 'vddarm', so that we keep a better consistency with the other internal regulators: vdd1p1: 800 <--> 1375 mV at 1100 mV vdd3p0: 2800 <--> 3150 mV at 3000 mV vdd2p5: 2000 <--> 2750 mV at 2400 mV vddarm: 725 <--> 1450 mV at 1150 mV vddpu: 725 <--> 1450 mV at 1150 mV vddsoc: 725 <--> 1450 mV at 1200 mV Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Anson Huang 提交于
Thermal sensor needs pll3_usb_otg when measuring temperature, so we need to pass clk info to thermal driver. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Lothar Waßmann 提交于
Signed-off-by: NLothar Waßmann <LW@KARO-electronics.de> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Troy Kisky 提交于
Make the interrupts node slightly more readable. Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Troy Kisky 提交于
We will reference mipi_csi from board dts files. Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
Currently, all pinctrl setting nodes are defined in <soc>.dtsi, so that boards that share the same pinctrl setting do not have to define it time and time again in <board>.dts. However, along with the devices and use cases being added continuously, the pinctrl setting nodes under iomuxc becomes more than expected. This bloats device tree blob for particular board unnecessarily since only a small subset of those pinctrl setting nodes will be used by the board. It impacts not only the DTB file size but also the run-time device tree lookup efficiency. The patch moves all the pinctrl data into individual boards as needed. With the changes, the pinctrl setting nodes becomes local to particular board, and it makes no sense to continue numbering the setting for given peripheral. Thus, all the pinctrl phandler name gets updated to have only peripheral name in there. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Tim Harvey 提交于
Typically nodes are disabled by default and enabled when needed. Signed-off-by: NTim Harvey <tharvey@gateworks.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 13 1月, 2014 1 次提交
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由 Nicolin Chen 提交于
This reverts commit b1d27c79. Previously we switched the SSI scriprt to dual-fifo mode to reduce playback underrun issue, which is only included by SDMA firmware version 2. However, there are quite a lot people still using version 1 or default firmware in the ROM code of SoC while these two kinds of firmwares do not support the dual-fifo script and the audio function on their platform would be broken. Thus this patch provisionally reverts the dual-fifo script to the original single fifo script to meet all kinds of users' requirements, including the version 1/2 or inner ROM firmware. Reported-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com> Tested-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
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- 16 12月, 2013 1 次提交
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由 Nicolin Chen 提交于
Use dual-fifo sdma scripts instead of shared scripts for ssi on i.MX series. Signed-off-by: NNicolin Chen <b42378@freescale.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NVinod Koul <vinod.koul@intel.com>
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- 18 11月, 2013 1 次提交
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由 Shawn Guo 提交于
The spdif "rxtx5" clock option is being set to ipg clk (62) by mistake. This causes an incorrect time keeping when spdif driver is running, because ipg is ancestor clock for clocksource while spdif driver will change the rate of this clock in certain circumstance. Before the correct clock for "rxtx5" option can be supplied, let's disable this option for now by filling a dummy clock for it. Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 29 9月, 2013 1 次提交
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由 Sean Cross 提交于
Add pcie device node for imx6qdl. Signed-off-by: NSean Cross <xobs@kosagi.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 26 9月, 2013 2 次提交
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由 Dong Aisheng 提交于
This is needed for supporting ultra high speed cards like SD3.0 cards. Signed-off-by: NDong Aisheng <b29396@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Reviewed-by: NNicolin Chen <b42378@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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- 22 8月, 2013 9 次提交
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由 Shawn Guo 提交于
The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB. Let's have separate node for imx6q and imx6dl. It also changes imx6q size 0x3f000 to 0x40000 to match the hardware. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NLiu Ying <Ying.Liu@freescale.com>
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由 Shawn Guo 提交于
Updates SSI nodes to adopt generic DMA bindings. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
Mark ocotp as a syscon node and add tempmon for imx6q thermal support. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
After mxs-dma driver adopts generic DMA device tree binding, gpmi channel interrupt number is defined in DMA controller node, and channel ID is listed in "dmas" property. So the DMA channel interrupt number in gpmi node "interrupts" property and fsl,gpmi-dma-channel which are used by old customized DMA binding can be removed now. Signed-off-by: NShawn Guo <shawn.guo@linaro.org> Reviewed-by: NArnd Bergmann <arnd@arndb.de>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Huang Shijie 提交于
Add the dma property for all the uart. Note: Add the dma property does not mean we enable the dma for this uart. Signed-off-by: NHuang Shijie <b32955@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Huang Shijie 提交于
Add the a new pinctrl for uart3. In the imx6q{dl}-sabreauto boards, the uart3 is used for Bluetooth. Signed-off-by: NHuang Shijie <b32955@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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由 Shawn Guo 提交于
Add more imx6q/dl pin groups for those supported boards, e.g. sabresd, sabreauto, arm2. IPU2 pin groups are added into imx6q.dtsi, since the block is only available on imx6q. Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
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